System and method for performing simultaneous read and write operations in memory

Abstract

A memory includes a set of content memory banks, a parity memory bank, and registers corresponding to the parity memory banks. The first memory interface device is configured to, in response to receiving a write request for writing to a set of content memory banks, perform a write operation over a plurality of clock cycles, including when parity information is written to the parity The memory bank previously temporarily stored parity information corresponding to the write request in the register. The second memory interface device is configured to, in response to i) receiving a read request for reading data from a memory bank in the set of content memory banks, and ii) determining that information responsive to the read request is to be read using parity information is reconstructed, and selectively uses information from i) a register or ii) a parity memory bank, to reconstruct information in response to a read request.

Description

[0001] Cross References to Related Applications [0002] This application claims U.S. Provisional Application No. 62 / 089,428, filed December 9, 2014, entitled "Write Routine During XOR Operations without Back Pressing NonWriting Interfaces," the entire disclosure of which is hereby incorporated by reference herein rights and interests. technical field [0003] The present disclosure relates generally to computer memory, and more particularly to memory devices having multiple memory banks and storing parity information to support multiple simultaneous memory accesses. Background technique [0004] The background description provided herein is for the purpose of generally presenting the context of the disclosure. The work of the presently named inventors is neither expressly nor impliedly admitted to the extent that the work is described in this Background section and aspects of the description that may not otherwise be limited to prior art at the time of filing is prior ar...

AI Technical Summary

Problems solved by technology

[0006] However, limitations in conventional memory devices on the ability of multiple devices and cores to quickly read data stored in shared memory or write data to shared memory may, for example, result in reduced switching capabilities

While each device can be provided with its own corresponding memory, such a solution is expensive both in terms of the direct cost of the additional memory and in terms of the resources required to keep the different memories synchronized

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