Multi-threshold voltage transistor and method of forming same

Abstract

Disclosed are a multi-threshold voltage transistor and a method of forming the same. The method comprises the steps of providing a substrate having, on the surface thereof, an interlayer dielectric layer and a first opening, a second opening, a third opening, a fourth opening, a fifth opening and a sixth opening that penetrate through the interlayer dielectric layer, first ions being doped in the substrate and on the bottoms of the first opening and the second opening and second ions being doped in the substrate and on the bottoms of the fourth opening and the fifth opening bottom; sequentially forming, on the sidewalls and bottoms of the six openings, a first P-type work function layer, a first barrier layer and a second P-type work function layer in a laminated manner; after removing the second P-type work function layer in the first, fourth, fifth and sixth openings, removing the first barrier layer in the fourth, fifth and sixth openings; sequentially forming a first N-type work function layer and a second N-type work function layer in a laminated manner on the sidewalls and bottoms of the six openings; and removing the second N-type work function layer in the first, second, third and fourth openings. The method simplifies the process and improves the performance.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a multi-threshold voltage transistor and a forming method thereof. Background technique [0002] A Complementary Metal-Oxide Semiconductor (CMOS) transistor is one of the basic semiconductor devices constituting an integrated circuit. The complementary metal-oxide-semiconductor transistor includes: a P-type metal-oxide-semiconductor (PMOS) transistor and an N-type metal-oxide-semiconductor (NMOS) transistor. [0003] In order to reduce and adjust the threshold voltage of the PMOS transistor and the NMOS transistor, a corresponding work function layer is formed on the surface of the gate dielectric layer of the PMOS transistor and the NMOS transistor. Wherein, the work function layer of the PMOS transistor needs to have a higher work function, while the work function layer of the NMOS transistor needs to have a lower work function. In the PMOS transistor and the NMOS t...

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Problems solved by technology

[0005] However, the process of multi-threshold voltage transistors formed in the prior art is complicated

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