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Trench-isolated native device compatible with cmos process and manufacturing method thereof

A technology of trench isolation and manufacturing methods, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as not providing

Active Publication Date: 2018-02-06
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, native devices that do not provide trench isolation in conventional CMOS processes

Method used

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  • Trench-isolated native device compatible with cmos process and manufacturing method thereof
  • Trench-isolated native device compatible with cmos process and manufacturing method thereof
  • Trench-isolated native device compatible with cmos process and manufacturing method thereof

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Embodiment Construction

[0022] See figure 2 In this application, the trench isolation native device compatible with the CMOS process is a deep n-well 11 buried in the p-type silicon substrate 10. On the p-type silicon substrate 10, there are a gate oxide layer 12, a gate 13 and a sidewall spacer 16. The sidewall spacers 16 are located on both sides of the gate oxide layer 12 and the gate 13. The surface of the p-type silicon substrate 10 under the two sides of the gate 13 has n-type heavily doped source and drain implanted regions 17. An n-type lightly doped drain implanted region 15 is provided inside the source drain implanted region 17. There is a p-type lightly doped drain implanted region 14 below the source drain implanted region 17. The bottom of the p-type lightly doped drain implantation region 14 contacts the upper surface of the deep n-well 11.

[0023] The innovation of the trench-isolated native device compatible with the CMOS process of this application is embodied in: a new deep n-wel...

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Abstract

The invention discloses a channel-isolated primary device compatible with a CMOS technology. A deep n trap is newly added in a p type silicon substrate, so that isolation of a channel and the substrate is achieved, and meanwhile a p type light dope leakage injection zone is newly added above the deep n trap and below a source-leakage injection zone, so that isolation of the source-leakage injection zone and the deep n trap is achieved. The channel-isolated primary device is similar to a common MOSFET, the deep n trap is used for isolation between the channel and the substrate, a PMOS in the CMOS technology and a p type input-output zone are newly added into the channel-isolated primary NMOS device for isolation of a source-leakage part and the deep n trap, the threshold voltage of about 0 V of the device is achieved, and the short circuiting phenomenon of the source-leakage part through the deep n trap is avoided.

Description

Technical field [0001] This application relates to a native device, in particular to a trench-isolated native device. Background technique [0002] The native device is a MOSFET (metal-oxide-semiconductor field effect transistor). Unlike general MOSFETs which are fabricated in n-wells or p-wells, native devices are directly fabricated on silicon substrates. The formation of the n-well or p-well of a general MOSFET includes well ion implantation, anti-punchthrough ion implantation, and channel ion implantation. The native device directly uses the silicon substrate as the channel without any well ion implantation, reverse punch-through ion implantation, and channel ion implantation. The 106th issue of "Electronics Monthly" published in Taiwan in May 2004 contains an article "The Electrostatic Discharge Protection Method of Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits in Nano-Processing", the third part of which is "Already-on( Native) component and its char...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06H01L21/336
CPCH01L29/0653H01L29/66477
Inventor 钱文生
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP