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Multi-threshold voltage fin field effect transistor and method of forming the same

A fin field effect, multi-threshold voltage technology, applied in transistors, electro-solid devices, circuits, etc., can solve problems such as poor electrical performance of transistors

Active Publication Date: 2020-03-10
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, the electrical performance of the multi-threshold voltage FinFETs formed in the prior art is poor

Method used

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  • Multi-threshold voltage fin field effect transistor and method of forming the same
  • Multi-threshold voltage fin field effect transistor and method of forming the same
  • Multi-threshold voltage fin field effect transistor and method of forming the same

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Embodiment Construction

[0037] As mentioned in the background art, the multi-threshold voltage fin field effect transistor formed in the prior art has poor electrical performance.

[0038] A method for forming a multi-threshold voltage fin field effect transistor, comprising: providing a semiconductor substrate, the surface of the semiconductor substrate has fins, and the semiconductor substrate and the fins have an interlayer dielectric layer and a penetrating interlayer dielectric The first opening, the second opening, the third opening, the fourth opening, the fifth opening, and the sixth opening of the layer, the first opening, the second opening, and the third opening correspond to the formation of N-type fin field effect transistors, and the fourth opening The opening, the fifth opening, and the sixth opening correspond to the formation of the P-type fin field effect transistor. The fins at the bottom of the first opening, the second opening, and the third opening are doped with first ions, and ...

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Abstract

The invention discloses a threshold-voltage fin-type field effect transistor and a forming method therefor. Through combining the difference of effective function values of a third work function layerrelative to a first work function layer and a second work function layer and the concentration difference of first ions, doped in the bottom fins, of a first opening relative to a second opening, themethod achieves the difference of threshold voltages of formed fin-type field effect transistors corresponding to the first opening, the second opening and the third opening. Through combining the difference of effective function values of a sixth work function layer relative to a fourth work function layer and a fifth work function layer and the concentration difference of second ions, doped inthe bottom fins, of a fourth opening relative to a fifth opening, the method achieves the difference of threshold voltages of formed fin-type field effect transistors corresponding to the fourth opening, the fifth opening and the sixth opening. Therefore, the method improves the electrical performances of the fin-type field effect transistors.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a multi-threshold voltage fin field effect transistor and a forming method thereof. Background technique [0002] A Complementary Metal-Oxide Semiconductor (CMOS) transistor is one of the basic semiconductor devices constituting an integrated circuit. The complementary metal-oxide-semiconductor transistor includes: a P-type metal-oxide-semiconductor (PMOS) transistor and an N-type metal-oxide-semiconductor (NMOS) transistor. [0003] In order to reduce and adjust the threshold voltage of the PMOS transistor and the NMOS transistor, a corresponding work function layer is formed on the surface of the gate dielectric layer of the PMOS transistor and the NMOS transistor. Wherein, the work function layer of the PMOS transistor needs to have a higher work function, while the work function layer of the NMOS transistor needs to have a lower work function. In the PMOS transist...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238H01L27/092H01L29/10
CPCH01L21/823821H01L21/823842H01L27/0924
Inventor 神兆旭居建华俞少峰刘洋李永明
Owner SEMICON MFG INT (SHANGHAI) CORP