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Integrated clip and lead and method of making circuit

A technology of circuits and leads, which is applied in the field of integrated fixtures and leads and the production of circuits, which can solve the problems of circuits and devices that cannot work and are prone to breakage

Active Publication Date: 2018-01-26
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, these bonds are susceptible to cracking and other failures, which can render circuits and devices inoperable

Method used

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  • Integrated clip and lead and method of making circuit
  • Integrated clip and lead and method of making circuit
  • Integrated clip and lead and method of making circuit

Examples

Experimental program
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Embodiment Construction

[0014] figure 1 is a side cross-sectional view of a portion of electronic device 100 showing the bond between clip 102 and lead 104 . Examples of device 100 include integrated circuits in quad flat no-lead (QFN) packages or dual flat no-lead (DFN) packages. Clip 102 is a conductive material such as copper that is coupled to at least one electronic component ( figure 1 not shown). In some embodiments, clip 102 is electrically coupled to the source or drain of at least one field effect transistor (FET). Leads 104 are also conductive material and serve as leads of device 100 to couple device 100 to other electronic devices. For example, leads 104 may electrically and mechanically couple device 100 to conductors on a printed circuit board.

[0015] The device 100 is embedded in a mold 106 applied by conventional molding techniques. Leads 104 have surfaces 107 not surrounded by mold 106 and serve as conductive pads for device 100 . During assembly of device 100 to a printed c...

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PUM

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Abstract

A circuit includes a conductive clip (502) coupled to at least one component in the circuit. At least one lead portion (552) is located on an end of the clip. The circuit further includes a first leadframe having at least one opening sized (444) to receive the at least one lead portion (552). The at least one lead portion (552) is received in the at least one opening (444), and the at least one lead portion (552) is an external conductor of the circuit.

Description

Background technique [0001] Some integrated circuits have leadless packages, such as quad flat no-lead (QFN) devices and dual flat no-lead (DFN) devices that physically and electrically couple the integrated circuit to a printed circuit board. Flat no-lead devices (also known as micro-leadframe (MLF) devices and small-outline no-lead (SON) devices) are based on surface-mount technology, which attaches integrated circuits to the surface of a printed circuit board without the need for a printed circuit through holes in the board. In some examples, a flat no-lead package is a near-chip-sized plastic-encapsulated package, typically fabricated with a planar copper leadframe substrate. Perimeter lands on the package provide electrical coupling to the printed circuit board. The pads serve as contacts and may be referred to as leads inside the integrated circuit, but these leads do not extend beyond the boundaries of the integrated circuit package. [0002] Some integrated circuits...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/495H01L27/00H01L21/60
CPCH01L23/492H01L23/4952H01L23/49551H01L23/49575H01L2924/181H01L2224/40245H01L2224/37147H01L2924/00014H01L24/37H01L2224/84801H01L24/38H01L23/49537H01L24/84H01L2924/00012H01L2224/8485H01L21/78H01L21/561H01L21/565H01L23/49524H01L23/49861H01L24/40
Inventor M·涩谷M·吉野
Owner TEXAS INSTR INC
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