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Method for solving computer cache coherency conflict

A consistent and computer-based technology, applied in the computer field, can solve problems such as protocol inefficiency, achieve high protocol efficiency, speed up the completion of read commands, and reduce redundant messages

Inactive Publication Date: 2018-02-09
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] Existing problem in the prior art mainly is that there is redundant message to produce when early conflict occurs; When late conflict occurs, CPU core also will send conflict confirmation message to notify main memory management end after obtaining the latest data, main memory After receiving this message, the management end sends the monitoring message (snp) to the CPU core again, so that the latest data of the CPU core is sent to the main memory management end, and the protocol is not efficient

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  • Method for solving computer cache coherency conflict

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Embodiment

[0020] Such as figure 1 As shown, a method for solving computer cache coherency conflicts includes steps:

[0021] S01, the CPU core read command terminal sends a read command to the read main memory management terminal, and records the issued command;

[0022] S02. The read main memory management terminal generates monitoring or reads main memory data according to the data location information.

[0023] The read main memory management end receives the command, and determines whether to send a monitoring message to the CPU core read command end according to the latest data position recorded in the data position information; if the data is in the memory, it will directly read the data from the memory; if the data is in the In the CPU, send a monitoring message to the CPU; if the data is in the main memory, read it, and send a completion message (cmp) to the CPU core read command terminal.

[0024] S03. The CPU core read command terminal generates corresponding actions accordi...

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Abstract

The embodiment of the invention provides a method for solving a computer cache coherency conflict. The method comprises the following steps that: a CPU (Central Processing Unit) kernel read command side emits a read command to a main memory management side and records the emitted command; a reading main memory management side generates monitoring or reading main memory data according to data position information; the CPU kernel read command side generates a corresponding action according to the recorded emitted command and the received message; after the reading main memory management side receives a conflict response message, a conflict response retransmission message is returned; the read command side judges early conflicts and late conflicts according to the received conflict response transmission message and a message finishing sequence; and the reading main memory management side receives a corresponding read finishing command. By use of the embodiment of the invention, during theearly conflict, redundant messages generated by the CPU kernel read command side are reduced; and during the late conflict, the CPU kernel does not need to obtain a conflict type to the reading memory management side, the finishing speed of the read command is quickened, and a protocol is more efficient.

Description

technical field [0001] The present invention relates to the field of computers. Background technique [0002] In the computer field, the core speed of the CPU is getting faster and faster, and it is developing towards multi-core. When a multi-core CPU accesses the consistent main memory, it needs to ensure that the data read by any CPU core must be the latest data. If the data is guaranteed to be in the main memory or the CPU core, the bus protocol layer is relatively simple, but it is possible that the data is on the way to the CPU core. In this case, there is a conflict of cache consistency. The conflict is divided into early conflict and late conflict. [0003] Early conflict means that the read request sent by the CPU to the main memory has not yet been completed. At this time, the CPU receives the conflict response (rspcnflt) generated by monitoring, which is an early conflict. In the early conflict, after the CPU receives the response, if a conflict occurs, it will se...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/50
CPCG06F9/5016
Inventor 刘刚
Owner ZHENGZHOU YUNHAI INFORMATION TECH CO LTD