Semiconductor structure manufacturing method and semiconductor structure
A semiconductor and isolation structure technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve the problems of reduced active area area of device unit area, reduced device performance, and increased process difficulty, so as to improve device performance , Reduce device disconnection and improve production yield
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0051] see figure 2 , the invention provides a kind of preparation method of semiconductor structure, the preparation method of described semiconductor structure comprises the following steps at least:
[0052] 1) A semiconductor substrate is provided, the semiconductor substrate includes a device unit area and a peripheral unit area located on the periphery of the device unit area;
[0053] 2) forming a barrier layer on the upper surface of the device unit region;
[0054] 3) Under the protection of the barrier layer, the structure obtained in step 2) is subjected to semiconductor oxidation treatment, so as to form a gate oxide layer on the upper surface of the peripheral cell region.
[0055] Please refer to figure 2 Step S1 in and image 3 , first perform step 1), providing a semiconductor substrate 1 , the semiconductor substrate 1 includes a device unit area 11 and a peripheral unit area 12 located on the periphery of the device unit area 11 .
[0056] As an example...
Embodiment 2
[0075] Such as Figure 8 As shown, the present invention also provides a semiconductor structure, and the semiconductor structure of this embodiment is prepared according to the preparation method of the semiconductor structure of the first embodiment. Specifically, the semiconductor structure includes: a semiconductor substrate 1, a first shallow trench isolation structure 13a, a second shallow trench isolation structure 13b, and a gate oxide layer 22; the semiconductor substrate 1 includes a device cell region 11 and a The peripheral cell region 12 on the periphery of the device cell region 11; the first shallow trench isolation structure 13a is located in the device cell region 11, and several first active regions are isolated in the device cell region 11 10a; wherein, the first active region 10a is completely adjacent to the first shallow trench isolation structure 13a; the second shallow trench isolation structure 13b is located in the peripheral cell region 12, and in th...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


