A Comparator and Successive Approximation Analog-to-Digital Converter

A comparator and inverter technology, used in analog/digital conversion, code conversion, instruments, etc., can solve problems such as low speed of comparators, and achieve the effect of increasing speed and reducing the number of

Active Publication Date: 2021-08-06
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the above comparator suffers from slow speed

Method used

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  • A Comparator and Successive Approximation Analog-to-Digital Converter

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Embodiment Construction

[0023] The asynchronous successive approximation analog-to-digital converter (Successive Approximation Register Analog-to-Digital Converter, SAR DC) is a research hotspot in recent years. Compared with the traditional pipelined ADC, the asynchronous SAR ADC has the advantages of low power consumption and low cost , These advantages enable asynchronous SAR ADC to obtain a wide range of applications, such as portable battery-powered instruments, pen input quantizers, industrial control and data signal collectors, etc.

[0024] However, the asynchronous SAR ADC also has the problem of low maximum operating speed, and the reason for the low maximum operating speed of the SAR ADC is its internal comparator.

[0025] Currently, a typical comparator structure is as figure 1As shown, the comparator includes: a first pre-op-amp unit 11 suitable for sequentially amplifying the signal to be compared at various stages, including an op-amp subunit 121 and an op-amp subunit 121 symmetricall...

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PUM

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Abstract

A comparator and a successive approximation analog-to-digital converter, the comparator includes: a sequentially connected pre-op amplifier circuit and a latch circuit, the pre-op amplifier circuit includes sequentially connected and suitable for amplifying signals to be compared The first, second, and third pre-op-amp units; the third pre-op-amp unit includes: first and second PMOS transistors; the latch circuit includes: a first CMOS inverter and The second CMOS inverter is provided with a bistable structure connected from end to end of the inverter, and is suitable for comparing the signals, and outputs a corresponding digital signal according to the comparison result; the first and second PMOS transistors The gate of the gate is coupled to the output end of the second pre-op amplifier unit; the gate of the first NMOS transistor and the gate of the second NMOS transistor are connected to the output end of the second pre-op amplifier unit and The input end of the third pre-op amplifier unit is coupled. By adopting the above solution, the speed of the comparator can be increased.

Description

technical field [0001] The invention relates to the technical field of integrated circuit devices, in particular to a comparator and a successive approximation analog-to-digital converter. Background technique [0002] Analog-to-Digital Converter (ADC) is the core module of today's applied electronic equipment and communication equipment. Due to the demand for portable electronic communication equipment in the electronic market in recent years, ADCs with low power consumption and high precision have become ADCs. Major trends in technology. As one of the main modules of the ADC structure, the comparator, especially the comparator with high speed and low power consumption, also plays an important role in the application market. [0003] Currently, a typical comparator structure is as figure 1 As shown, the comparator includes: a first pre-op amp unit 11, a second pre-op amp unit 12, and a third pre-op amp unit 13, which are suitable for sequentially amplifying the signals to...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K5/24H03M1/46
CPCH03K5/2481H03M1/462
Inventor 荀本鹏刘飞徐丽唐华杨海峰
Owner SEMICON MFG INT (SHANGHAI) CORP
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