Real-time fault injection timing sequence resource optimization method and system thereof

Abstract

The invention relates to the technical field of power electronic digital simulation, and discloses a real-time fault injection timing sequence resource optimization method and a system thereof, so asto solve the FPGA timing sequence error problem under the fault injection situation, and optimize the FPGA logic resource, which can be used to provide a stable and reliable simulation environment forreal-time simulation and fault injection of a high-speed train transmission control system. The method comprises steps of establishing a transmission system model; analyzing the sequential logic circuit of a corresponding transmission system model by using an FPGA development platform; traversing all the timing sequence start and end pairs in the sequential logic circuit and combination logic circuits between them; establishing a timing sequence directed graph G[0] in the normal running state and an initial timing directed graph G[fn](0) in the fault running state of the transmission system model; traversing a time margin of each timing sequence path in the G[0] and a time margin of each timing sequence path in the G[fn](0); and iteratively updating the time margin of each timing sequencepath in the G[fn](0) until the time margin of each timing sequence path meets the requirements.

Description

technical field [0001] The invention relates to the technical field of power electronics digital simulation, in particular to a real-time fault injection timing resource optimization method and system thereof. Background technique [0002] With the continuous development of modern rail transit technology, the safety of high-speed trains has become the primary issue in the operation and development of high-speed railways. As one of the key systems for the safety of high-speed train operation, the transmission control system is also one of the main sources of high-speed train failures. , in order to ensure the safe and reliable operation of the transmission control system, reduce R&D costs, shorten the development cycle and on-board debugging time, and reduce the verification time, all fault diagnosis technologies must be verified by real-time simulation experiments in the laboratory before they are put into operation. [0003] At present, most of the existing real-time simula...

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Problems solved by technology

[0003] At present, most of the existing real-time simulation experiments adopt the hardware-in-the-loop simulation method, in which field programmable logic gate FPGA is widely used in the hardware-in-the-loop simulation experiment. Quickly solve the ordinary differential equations in the model, but because the main circuit of the transmission control system includes multiple component models such as transformers, converters, and motors, the model solving process takes up a lot of FPGA logic resources, especially in real-time When fault injection, adding fault injection signal model will bring a series of problems, such as the timing error of model solution, and increase the occupancy of FPGA logic resources

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