Method, device, computer equipment and storage medium for estimating the number of erroneous bits

A technology of error bits and number, applied in the field of error bit number estimation method, device, computer equipment and storage medium, can solve the problems of inability to reduce the number of retries, increase, data read and write errors, etc., to reduce decoding The number of iterations and retries, and the effect of improving decoding efficiency

Active Publication Date: 2022-03-29
SHENZHEN YILIAN INFORMATION SYST CO LTD
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Problems solved by technology

[0002] Due to the shortcomings of solid-state drives that are prone to data read and write errors, the probability of data errors increases significantly after a large number of erases and writes. Therefore, it is very necessary to ensure the error correction algorithm. For example, the solid-state drive uses the ECC algorithm to verify and change data errors. , and judging whether it is a bad block, and accurately estimating the number of error bits is of great significance for estimating the quality of the channel environment, but the error correction ability of the error correction algorithm is basically fixed, and there is no more suitable algorithm that can accurately Estimate the number of error bits of the code word before entering the LDPC decoder, and then cannot reduce the number of retries, making the decoding efficiency low,

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  • Method, device, computer equipment and storage medium for estimating the number of erroneous bits
  • Method, device, computer equipment and storage medium for estimating the number of erroneous bits

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Embodiment Construction

[0070] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0071] It should be understood that when used in this specification and the appended claims, the terms "comprising" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude one or Presence or addition of multiple other features, integers, steps, operations, elements, components and / or collections thereof.

[0072] It should also be understood that the terminology used ...

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Abstract

The present invention relates to a method, a device, a computer device and a storage medium for estimating the number of error bits. The method includes counting the number of test error bits in a set interval and the number of corresponding syndromes not satisfied by the test; establishing an initial model according to the statistical results ;Fit the initial model to form a target model; calculate the actual number of unsatisfied syndromes for the codeword input into the decoder when in use; use the target model and the actual number of unsatisfied syndromes to estimate the actual number of error bits number. The present invention obtains target models in different intervals by counting the number of test error bits in the set interval and the corresponding number of unsatisfied syndromes in the test. The target model in which the number falls into the interval estimates the actual number of error bits, effectively selects the decoding mode or directly performs the next read retry, reduces unnecessary decoding iterations and the number of retries, and can improve the overall decoding efficiency.

Description

technical field [0001] The invention relates to a solid-state hard disk, and more specifically refers to a method, a device, a computer device and a storage medium for estimating the number of error bits. Background technique [0002] Due to the shortcomings of solid-state drives that are prone to data read and write errors, the probability of data errors increases significantly after a large number of erases and writes. Therefore, it is very necessary to ensure the error correction algorithm. For example, the solid-state drive uses the ECC algorithm to verify and change data errors. , and judging whether it is a bad block, and accurately estimating the number of error bits is of great significance for estimating the quality of the channel environment, but the error correction ability of the error correction algorithm is basically fixed, and there is no more suitable algorithm that can accurately Estimate the number of error bits of the code word before entering the LDPC dec...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/07
CPCG06F11/0727G06F11/0751G06F11/079G06F11/0793
Inventor 管金新郭超
Owner SHENZHEN YILIAN INFORMATION SYST CO LTD
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