FINFET structure with controllable air gaps

Abstract

The present disclosure provides a method that includes forming an isolation feature in a semiconductor substrate; forming a first fin and a second fin on the semiconductor substrate, wherein the firstand second fins are laterally separated by the isolation feature; and forming an elongated contact feature landing on the first and second fins. The elongated contact feature is further embedded in the isolation feature, enclosing an air gap vertically between the contact feature and the isolation feature. The invention also relates to a FinFET structure with controllable air gaps.

Description

technical field [0001] Embodiments of the invention relate to FinFET structures with controllable air gaps. Background technique [0002] In semiconductor technology, various integrated circuit components, such as doped regions and gate stacks, are formed on a substrate by various processes including photolithography, ion implantation, etching and deposition. Interconnect structures, including various conductive features such as contact features, via features, and metal lines, are formed and configured to connect integrated circuit components into functional circuits. For example, a damascene process may be utilized to form multilayer copper interconnects. However, existing approaches can cause various problems such as parasitic capacitance and bridging (leakage), which can adversely affect circuit performance (such as introducing additional time delays or causing circuit failures). In particular, as semiconductor technology progresses to advanced technology nodes with sma...

AI Technical Summary

Problems solved by technology

However, existing methods cause various problems such as parasitic capacitance and bridging (leakage), which can adversely affect circuit performance (such as introducing additional time delays or causing circuit failures)

In particular, as semiconductor technology progresses to advanced technology nodes with smaller feature sizes, such as 20nm, 16nm or less, the problem of parasitic capacitance is further exacerbated, which further leads to degradation of circuit performance and reliability

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