A Robust Design Method for Non-Standard Input VESA Timing

A design method and a robust technology, applied in the field of video processing, can solve problems such as bad processing methods, robustness of the output screen, abnormal output screen, etc., and achieve the effect of easy hardware logic implementation, clear design structure, and stable output state

Active Publication Date: 2021-07-09
LUOYANG INST OF ELECTRO OPTICAL EQUIP OF AVIC
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  • Abstract
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  • Application Information

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Problems solved by technology

However, in the process of image conversion and processing, because the input VESA timing sequence does not necessarily fully comply with the VESA standard timing sequence, the logic has a great impact on the robustness of the output screen by the way the input VESA protocol data is processed.
Bad processing methods may lead to abnormal output screen

Method used

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  • A Robust Design Method for Non-Standard Input VESA Timing
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  • A Robust Design Method for Non-Standard Input VESA Timing

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Embodiment Construction

[0022] Embodiments of the present invention are described in detail below, and the embodiments are exemplary and intended to explain the present invention, but should not be construed as limiting the present invention.

[0023] In the standard vesa timing, VS, HS, and DE have strict timing correspondence. However, in the actual circuit, the input VESA timing does not fully meet the VESA timing standard. The common non-standard input VESA timing has the following situations (take the resolution of 1280*1024@60Hz as an example):

[0024] 1. VS and HS do not change to high level at the same clock rising edge;

[0025] 2. One line is not equal to 1688 clock cycles (the number of effective pixels is 1280);

[0026] 3. The number of lines in the blanking period is not equal to 42 lines (the effective number of DE lines is 1024);

[0027] 4. DE high level time is not equal to 1280 clocks.

[0028] 5. The number of input lines is not equal to 1024 lines.

[0029] Due to the logic ...

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Abstract

The invention proposes a robust design method for non-standard input vesa timing. First, count the lines of the effective video signal DE in the input VESA timing signal to judge whether a frame of data is complete; then use the synchronous processing mechanism to perform clock synchronization processing on the effective video signal DE and video data signal QE; finally, use each input vesa A DE rising edge is used as a reference, and a three-stage state machine mechanism is used to generate standard DE effective timing and relatively standard HS and VS timing according to VESA standard timing parameters. The invention can convert the non-standard vesa timing into a relatively standard vesa timing, and ensure that the effective data signal and video data meet the vesa timing standard.

Description

technical field [0001] The invention relates to the technical field of video processing, in particular to the conversion of VESA timing, in particular to a robust design method for non-standard input VESA timing. Background technique [0002] At present, pre-distortion technology is generally used in civil aircraft head-up display and other digital head-up display to preprocess the input video image to eliminate the distortion of the optical system. However, in the process of image conversion and processing, since the input VESA timing sequence does not necessarily fully comply with the VESA standard timing sequence, the logic has a great impact on the robustness of the output image by the way the input VESA protocol data is processed. Bad processing methods may lead to abnormal output screen. It is necessary to propose a robust design method for non-standard input VESA timing, and correct the input non-standard timing to ensure the correctness of the VESA timing output to ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N5/04H04N5/06H04N5/14
CPCH04N5/04H04N5/06H04N5/14
Inventor 赵学娟苏霖王全忠
Owner LUOYANG INST OF ELECTRO OPTICAL EQUIP OF AVIC
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