A verification method of soc chip

Abstract

The invention discloses a verification method for SoC chips, which belongs to the technical field of chip testing. The output port is taken over; in step S2, the monitor is used to read the input and output behavior of each master-level device and transmit it to the scoreboard; step S3, the monitor is used to read the input and output data of the slave-level equipment corresponding to each master-level device and transmit it Go to the scoreboard; step S4, verify the correlation between the input and output behavior of each master device and the input and output data of the corresponding slave device through the scoreboard according to the preset test standard, and output the verification result. The beneficial effects of the above technical solutions are: covering all function points of the chip, simplifying the verification process, and improving the verification efficiency.

Description

technical field [0001] The invention relates to the technical field of chip testing, in particular to a verification method for SoC chips. Background technique [0002] A SoC (System on Chip, system-on-chip) chip is an integrated circuit chip produced by an integrated design idea, and the SoC chip is integrated with the key components of the system required to complete the core functions of the system. In other words, the SoC chip can be regarded as a complete micro-miniature system integrated on a chip, which is usually customized by customers, or a standardized product for a specific purpose. [0003] At present, in all walks of life, SoC chips are generally used to realize the intelligent control of equipment. For example, in the field of vehicle control, the SoC chip is usually used to realize the control of the internal equipment of the vehicle, such as the control of the vehicle windows and instruments. Due to the high reliability requirements of SoC chips, the corre...

AI Technical Summary

Problems solved by technology

[0006] For the traditional SoC chip verification method, the function points that can be covered by direct stimulation are very limited. A complete verification requires a large number of direct verification stimulation, which requires a lot of manpower, and the reusability of test cases is low.

At the same time, the excitation output of each master level cannot traverse all possible situations, and the complete verification of the slave-level devices connected to the bus matrix cannot be performed in the SoC verification, which poses a great challenge to the verification work.

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