Write message prospect processing method and device facing board-level high-speed bus

Abstract

The invention discloses a write message prospect processing method and device facing a board-level high-speed bus. The method comprises the following steps: receiving a write message of a link layer; carrying out checking; setting error flag bits; requesting retransmission when the checking result shows that the message is unqualified; identifying the write command and the write data of the write message; caching the write command and the write data through an FIFO queue; outputting the write command and the write data to follow-up message processing logic; detecting the error flag bits of the write message; receiving retransmitted write messages when any error flag bit exists till no error flag bit exists; covering the cached write message if the FIFO queue is not empty; generating a new error correction write message if the FIFO queue is empty, and writing the new error correction write message into the FIFO queue. The device comprises a link layer receiving unit and a message cache and prospect processing unit which are related in the method. The method and device have the advantages that the performance of a storage system can be improved; distinguishing of types of write requests and write data in follow-up processing and cancellation of inaccurate write requests and data are voided; the logic design and verification in follow-up processing are simplified.

Description

technical field [0001] The invention relates to the technical field of message processing delay optimization of a board-level interconnection bus, in particular to a forward-looking processing method and device for writing messages facing a board-level high-speed bus. Background technique [0002] With the rapid development of the number of integrated cores on many-core processors, the processor's demand for storage system performance has doubled. At the same time, the performance improvement speed of mainstream DDRx memory lags far behind the demand growth rate. Therefore, a single processor equipped with more and more main memory channels has become the current mainstream solution. For example, IBM's power7 processor has 8 DDR3 channels, while the power8 processor has increased to 16 DDR3 channels. [0003] Since the DDR adopts a parallel bus interface, a DDR interface with a data width of 72 requires more than 150 IOs. A large number of DDR channels will exhaust limited...

AI Technical Summary

Problems solved by technology

The invalidation operation requires subsequent processing modules to add special logic for support, increasing the complexity of hardware design, and the final execution of the write request still needs to wait for the verification result, which cannot really eliminate the verification delay of the write request message

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