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Soc test code programming method, ip test method and device

A technology for testing codes and codes, which is applied in the direction of software testing/debugging, architecture with a single central processing unit, and general-purpose stored program computers, etc. It can solve the problems of low chip test coverage and achieve insufficient test coverage and save money. Effect of time, simplified process

Active Publication Date: 2022-04-01
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In order to solve the technical problem that part or all of the IP of the chip cannot be tested in Test Mode, resulting in low test coverage during mass production, the embodiment of the present invention provides a test code programming method, IP test method and device for SoC chips

Method used

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  • Soc test code programming method, ip test method and device
  • Soc test code programming method, ip test method and device
  • Soc test code programming method, ip test method and device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0063] A kind of test code burning method of SoC, such as figure 2 As shown, can include:

[0064] Step 201, cutting out the BOOT code, adding the code of the IP test case to the BOOT code, and corresponding the preset test instructions to the IP test case in the BOOT code, to obtain the test code;

[0065] Step 202, compiling the test code to generate a binary file;

[0066] Step 203, utilize the pre-written test pattern to write the binary file into the EMMC of the test platform by dynamic to static structure (Dynamic to Static, D2S) simulation Xmodem protocol, and the test pattern can include predefined combination information , the combined information includes predefined timing information and level information.

[0067] In this embodiment, the cutting BOOT code, before adding the code of the IP test case to the BOOT code, may also include: pre-configuring a test instruction set for SoC chip IP testing, the test instruction set includes at least one The test instructi...

Embodiment 2

[0100] The present embodiment provides a kind of IP test method of SoC chip, such as Figure 6 As shown, can include:

[0101] Step 601, the SoC chip obtains the test instruction from the test platform through the UART interface;

[0102] Step 602, the SoC chip loads the test code in the EMMC by the BOOT CPU, calls the corresponding IP test case of the test instruction and configures the registers, and completes the IP test;

[0103] Wherein, the test code includes IP test cases and corresponding test instructions.

[0104] In an implementation mode, the exemplary implementation process of the IP testing method of the above-mentioned SoC chip, such as Figure 7 As shown, can include:

[0105] Step 701, define a test instruction set, different instructions correspond to different IP test items, and different test cases can be invoked by sending instructions to the SoC during the test.

[0106] For example, taking High Definition Multimedia Interface (HDMI, High Definition M...

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PUM

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Abstract

This paper discloses a test code programming method of a SoC chip, an IP test method and a device. The test code programming method of the SoC includes: cutting the BOOT code, adding the code of the IP test case to the BOOT code, and In the BOOT code, the preset test instruction is corresponding to the IP test case to obtain the test code; the test code is compiled to generate a binary file; the pre-written test pattern is used to simulate the Xmodem protocol through D2S. The binary file is written into the embedded multimedia card EMMC of the test platform, and the test pattern includes predefined combination information, and the combination information includes predefined timing information and level information. This application simplifies the code upgrading process and saves the time for upgrading and testing codes.

Description

technical field [0001] The invention relates to the technical field of chip testing, in particular to a SoC chip testing code programming method, IP testing method and device. Background technique [0002] Generally speaking, a system on a chip (SoC, System on Chip) integrates a microprocessor, an analog IP core, a digital IP core, an interconnection bus, a memory, etc. (or an off-chip storage control interface) on a single chip, and it is usually a customized , or standard products for specific applications. In some special application scenarios, the test mode (TestMode) was not set during chip design, or some key pins were not packaged for cost considerations, and the IP cannot be tested in Test Mode, resulting in insufficient chip test coverage during mass production. Contents of the invention [0003] In order to solve the technical problem that part or all of the IP of the chip cannot be tested in Test Mode, resulting in low test coverage during mass production, the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/36G06F15/78
Inventor 鲁帅李光耀
Owner SANECHIPS TECH CO LTD
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