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Memory access method and hardware

A memory access and memory technology, applied in the protection of internal/peripheral computer components, memory systems, instruments, etc., to solve problems such as program performance degradation

Active Publication Date: 2019-09-03
HYGON INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this solution greatly reduces the number of caches that can be used by each code, so that the performance of programs that are sensitive to memory access will be severely degraded.

Method used

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  • Memory access method and hardware
  • Memory access method and hardware

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Embodiment Construction

[0020] Exemplary embodiments of the present disclosure will be described below with reference to the accompanying drawings. In the interest of clarity and conciseness, not all features of an actual implementation are described in this specification. However, it should be understood that many implementation-specific decisions can be made during the development of any such actual implementation in order to achieve the developer's specific goals, and that these decisions may vary from implementation to implementation .

[0021] Here, it should be noted that, in order to avoid obscuring the present disclosure due to unnecessary details, only the device structure closely related to the solution according to the present disclosure is shown in the drawings, and the structure related to the present disclosure is omitted. Other details that don't really matter.

[0022] It is to be understood that the present disclosure is not limited to only the described embodiments as described be...

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Abstract

The invention provides a memory access method and hardware. The performance of a program sensitive to memory access can be considered while a side channel attack based on a shared cache is prevented.The method comprises the steps that hardware acquires data of a private cache to be processed and a value of a first flag bit of a cache line of the private cache, wherein the value of the first flagbit corresponding to the data of the private cache sensitive to the side channel attack based on the shared cache indicates whether to allow the memory corresponding to the private cache sensitive tothe side channel attack based on the shared cache to use the shared cache; and when the value of the hardware at the first flag bit indicates that the memory corresponding to the corresponding privatecache is not allowed to use the shared cache, the data of the private cache which is not allowed to use the shared cache is directly written into the corresponding memory.

Description

technical field [0001] The invention relates to the technical field of computer security, in particular to a memory access method and hardware. Background technique [0002] In modern computer architecture, due to the huge gap between memory access speed and CPU execution speed, the emergence of cache is greatly reduced by saving the memory data that the computer has frequently accessed recently in a smaller cache that can be accessed quickly It reduces the number of direct CPU accesses to the memory and greatly improves the execution efficiency of the computer. [0003] On the other hand, with the gradual improvement of the theoretical system of computer cryptography and the gradual maturity of computer security software development, more and more known security problems have been gradually improved, and the problem of side channel attacks has gradually emerged. For example, the specter and fuse viruses that were exposed in 2017 are typical representatives of side channel ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/084G06F21/78
CPCG06F12/084G06F21/78
Inventor 杜朝晖应志伟
Owner HYGON INFORMATION TECH CO LTD