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Testing and automatic correction method, storage medium and terminal for assertion generality of formal verification

A formal verification and automatic correction technology, applied in electronic circuit testing, digital circuit testing, electrical measurement, etc., can solve problems such as reduced efficiency, causal ambiguity, lack of integrity, etc., and achieve the effect of increasing integrity and high efficiency

Active Publication Date: 2019-10-08
成都奥卡思微电科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

First, it only addresses causal emptiness, lacking completeness
Second, each assertion will do two verifications, reducing efficiency

Method used

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  • Testing and automatic correction method, storage medium and terminal for assertion generality of formal verification

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Embodiment Construction

[0027] The technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0028] The terminology used in this application is for the purpose of describing particular embodiments only, and is not intended to limit the application. As used in this application and the appended claims, the singular forms "a", "the", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed item...

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Abstract

The invention relates to a testing and automatic correction method, a storage medium and a terminal for assertion generality of formal verification. The method comprises: setting all sub expressions of the assertion to be 0 and 1 respectively; carrying out integration and carrying out minimization of the automaton to obtain two results; and determining that the assertion has generality under the condition of the same results. On the basis of the most general generality definition, the integrity of the test is enhanced; and because of the used integrated process and confirmability of minimization, the two results only need structural comparison, so that the efficiency is high.

Description

technical field [0001] The invention relates to a method for testing and automatically correcting the ambiguity of a formal verification assertion, a storage medium and a terminal. Background technique [0002] Formal verification is a chip function verification technology based on logical modeling and mathematical reasoning proof. It is a supplement to traditional simulation verification and is replacing simulation in many scenarios. Due to the uniqueness of formal verification technology, there are many obstacles in its application in the chip design verification process. The first one is how to generate correct and accurate assertions. There are two types of assertions: constraints and attributes. The former defines the input environment of the design under test, and the latter is the object of formal verification—that is, whether these properties are established under all operating states and operating paths of the design allowed by the input constraints. [0003] Due ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/317
CPCG01R31/31704
Inventor 袁军
Owner 成都奥卡思微电科技有限公司
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