Lag synchronization of cross clock domain

Abstract

The invention discloses a method and device for tracing delay of a signal, which is emitted from a first clock domain to a second clock domain. For example, at a first time, a public timing referencesignal (SysRef) is received in the first time domain, and a delay mark is inputted into a first-in-first-out (FIFO) data structure that couples the first time domain to the second time domain. At a second time, SysRef is received in the second time domain, and a timer is started in the second time domain. At a third time, the delay mark is received from FIFO in the second time domain, and a counter is stopped in final counting. Based on the final counting, and the difference between the second time and the first time, FIFO delay is determined.

Description

[0001] executive power [0002] This invention was made with administrative support, in part, under Agreement HR0011-16-3-0004 awarded by the Defense Advanced Research Projects Agency. The government has certain rights in this invention. technical field [0003] Aspects of the disclosure relate generally to integrated circuits, and more particularly to delays in systems including multiple clock domains. Background technique [0004] Circuits incorporating multiple data converters (such as analog-to-digital converters ADC and / or digital-to-analog converters ADC, etc.) may require precise synchronization of data streams, as well as synchronous control of associated data path controls. This synchronization may be necessary to ensure that data stream processing is applied deterministically. However, such circuits may include many independent clock domains. Data transfer between these clock domains can complicate timing synchronization. It may be desirable to ensure synchron...

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Problems solved by technology

However, such circuits may include many independent clock domains

Data transfer between these clock domains can complicate timing synchronization

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