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Gated diode having fingers with elevated gates

A technology of diodes and fingers, applied in the field of integrated circuits, can solve problems such as large occupied area

Pending Publication Date: 2020-03-13
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Thus, since the thickness of the P+ and N+ diffusers is determined by those other requirements, in order for a gated diode with the architecture of gated diode 200 to be able to support a sufficient amount of current for ESD protection, the gated diode must be designed into a sufficient number of fingers, where greater maximum current levels require more fingers, and thus a larger footprint on the semiconductor substrate for those gated diodes

Method used

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  • Gated diode having fingers with elevated gates
  • Gated diode having fingers with elevated gates
  • Gated diode having fingers with elevated gates

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Embodiment Construction

[0054] One aspect of the invention is an integrated circuit comprising a first gated diode comprising one or more diode fingers, each diode finger comprising a raised gate and a A p-type diffuser and an n-type diffuser on opposite sides. The p-type diffuser includes a p-type base region and a p-type annular side region between the p-type base region and the raised gate, and the n-type diffuser includes an n-type base region and an Raise the n-type ring-shaped side regions between the gates.

[0055] Another aspect of the invention is a method for fabricating a first gated diode for an integrated circuit. One or more diode fingers of a first gated diode are formed on the substrate, each diode finger including a raised gate and p-type and n-type diffusions on opposite sides of the raised gate body. The p-type diffuser includes a p-type base region and a p-type annular side region between the p-type base region and the raised gate, and the n-type diffuser includes an n-type ba...

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Abstract

An integrated circuit has a first gated diode with one or more diode fingers. Each diode finger has an elevated gate, an underlying p-type diffusion, and an underlying n-type diffusion. Each diffusionhas a base region and an annular side region located between the base region and the elevated gate such that the diffusions have increased lateral surface areas that support greater current levels for the diode finger, which enables gated diodes to be implemented with fewer fingers and therefore less layout area than equivalent conventional gated diodes that do not have elevated gates. The firstgated diode can be implemented with an analogous second gated diode to form ESD-protection circuitry for the integrated circuit.

Description

technical field [0001] The present invention relates to integrated circuits (ICs), and more particularly to IC diodes, such as those used for electrostatic discharge (ESD) protection. Background technique [0002] Integrated circuits are fabricated by selectively adding material to and removing material from a semiconductor substrate in a series of fabrication steps. For example, a p (positive) or n (negative) doped well region will remain undoped by masking, and then an appropriate p-type dopant material or n-type dopant material is applied to the remaining unmasked region A p / n well is formed on the substrate. During such fabrication steps, the p / n wells will all be formed to have the same thickness (also referred to as depth), which is determined by the requirements of the desired integrated circuit system. [0003] One known type of integrated circuit is ESD protection circuitry designed to protect other circuitry formed on the same substrate from electrostatic dischar...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02
CPCH01L27/0255H01L29/8611H01L29/66356H01L29/7391
Inventor 洪全敏尹春山陈瑜
Owner NXP BV
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