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Method for generating netlist through FPGA circuit verification and circuit logic verification platform

A technology of circuit netlist and circuit logic, which is applied in the field of FPGA circuits, can solve the problems of low verification efficiency and achieve the effect of shortening the duration of simulation verification

Active Publication Date: 2020-03-17
SHENZHEN PANGO MICROSYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The main technical problem to be solved is that when the FPGA chip circuit module is verified for the circuit to be tested, all the chip circuit netlist modules are released for verification, and the verification efficiency is low

Method used

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  • Method for generating netlist through FPGA circuit verification and circuit logic verification platform
  • Method for generating netlist through FPGA circuit verification and circuit logic verification platform
  • Method for generating netlist through FPGA circuit verification and circuit logic verification platform

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0037] In order to avoid the problem of low efficiency when verifying the FPGA chip circuit module of the circuit to be tested, all the chip circuit netlist modules are released for verification. The present invention provides a method for generating a netlist for FPGA circuit verification. The method for generating a netlist for FPGA circuit verification provided by the present invention will be described below with reference to embodiments.

[0038] See figure 1 , figure 1 This is a basic flowchart of the method for generating a netlist for FPGA circuit verification in this embodiment, and the method for generating a netlist includes:

[0039] S101. Obtain a circuit netlist of the FPGA circuit.

[0040] In this embodiment, all circuit netlists of FPGA full-chip circuits are acquired.

[0041] S102: Generate a layout file according to the circuit file to be tested.

[0042] In this embodiment, a software tool that generates bit streams is used to generate the layout file of the circui...

Embodiment 2

[0066] The method for generating a netlist for FPGA circuit verification of the present invention can realize the verification of the netlist module required by the FPGA chip circuit of the circuit to be tested when the circuit to be tested uses the FPGA chip circuit module for simulation verification, and shorten the simulation verification time. To facilitate understanding, the method for generating a netlist for FPGA circuit verification of the present invention will be described below in conjunction with an application scenario.

[0067] Figure 5 This is a detailed flowchart of the method for generating a netlist for FPGA circuit verification provided in the second embodiment of the present invention. The method for generating a netlist includes:

[0068] S501. Obtain a circuit netlist of the FPGA circuit.

[0069] In this embodiment, all circuit netlists of FPGA full-chip circuits are acquired.

[0070] S502: Generate a layout file according to the circuit file to be tested.

[0...

Embodiment 3

[0093] The method for generating a netlist for FPGA circuit verification of the present invention can realize the verification of the netlist module required by the FPGA chip circuit of the circuit to be tested when the circuit to be tested uses the FPGA chip circuit module for simulation verification, and shorten the simulation verification time. To facilitate understanding, the method for generating a netlist for FPGA circuit verification of the present invention will be described below in conjunction with an application scenario.

[0094] Image 6 This is a detailed flowchart of the method for generating a netlist for FPGA circuit verification provided in the third embodiment of the present invention. The method for generating a netlist includes:

[0095] S601. Obtain a circuit netlist of the FPGA circuit.

[0096] In this embodiment, all circuit netlists of FPGA full-chip circuits are acquired.

[0097] S602: Generate a layout file according to the circuit file to be tested.

[009...

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Abstract

The embodiment of the invention provides a method for generating a netlist through FPGA circuit verification and a circuit logic verification platform. A circuit netlist of an FPGA circuit is obtainedto generate a layout wiring file according to the to-be-tested circuit file, position information of a module required by a to-be-tested circuit in the FPGA circuit is acquired, an instance name of each module called by the FPGA circuit and a mapping relationship of a position coordinate of the instance name of each module in the FPGA circuit are obtained; and then an instance name of the required module or an instance name of the module to be shielded is obtained according to the position information of the required module and the mapping relationship, and finally a netlist of the required module is generated from the FPGA circuit netlist according to the instance name of the required module or the instance name of the module to be shielded. In some implementation processes, when the FPGA chip circuit module is used for simulation verification of the to-be-tested circuit, the netlist module needed by the to-be-tested circuit in the FPGA chip circuit can be verified, and the effect ofshortening the simulation verification duration is achieved.

Description

Technical field [0001] The embodiment of the present invention relates to the field of FPGA circuits, and specifically relates to but not limited to a method for generating a netlist for FPGA circuit verification and a circuit logic verification platform. Background technique [0002] FPGA (Field-Programmable Gate Array) chips play a pivotal role in communications, security, industry and other fields. With the gradual improvement of the process level, the scale of FPGA chips continues to expand, the performance continues to improve, and the verification workload also increases. [0003] The expansion of FPGA circuit scale means that the number of modules, the scale of the circuit netlist, and the complexity of the circuit are also increasing. Due to the limited operating speed of the simulation tool, the increase in the size of the netlist will lead to an increase in the simulation running time, resulting in a decrease in verification efficiency. In fact, during verification, mos...

Claims

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Application Information

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IPC IPC(8): G06F30/34G06F30/347
Inventor 李晓艳
Owner SHENZHEN PANGO MICROSYST CO LTD