Method and device for testing gate stack defects of three-dimensional memory

Abstract

The invention provides a test method and a test device for gate stack defects of a three-dimensional memory. The invention discloses a method for testing a three-dimensional memory, which belongs to the field of semiconductor design, manufacture and test, and comprises the following steps of: providing a three-dimensional memory gate stack which is provided with a channel hole, a memory film and apolycrystalline silicon channel are arranged in the channel hole, and the channel hole is at least provided with a channel part of which the aperture is reduced from the top to the bottom of the gatestack; and applying a plurality of stress voltages between the gate stack and the polysilicon channel, wherein the stress voltages are reduced along with the reduction of the aperture of the channelpart. According to the invention, the defect electric stress of the gate stack is screened; a plurality of stress voltages are applied between the gate stack and the polycrystalline silicon channel according to the actual morphology of the channel hole, and the stress voltages are reduced along with the reduction of the aperture of the channel hole, so that the stress voltage corresponding to thelarge-size storage region is large, the stress voltage corresponding to the small-size storage region is small, and the stress electric fields of all the storage layers are basically consistent.

Description

technical field [0001] The invention belongs to the field of semiconductor design, manufacture and testing, and in particular relates to a testing method and testing device for three-dimensional storage gate stack defects. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar flash memory and to pursue lower production costs per unit storage unit, a three-dimensional memory structure emerged as the times require. The three-dimensional memory structure can make each memory die in the memory device have more numbers. memory unit. [0003] In non-volatile memory, such as NAND memory, one way to increase memory density is by us...

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a testing method and testing device for three-dimensional memory gate stack defects, which are used to solve the problem of memory cell characteristic degradation or The problem that the stress voltage is too small to achieve the purpose of accelerating the failure of defects

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