Test method and test device for three-dimensional memory gate stack defects

Abstract

The invention provides a method and a testing device for testing defects in a gate stack of a three-dimensional memory, which belong to the field of semiconductor design, manufacture and testing. The test method includes the steps of: providing a gate stack of a three-dimensional memory, the gate stack having a channel hole, There is a memory film and a polysilicon channel in the channel hole, and the channel hole has at least one channel portion whose aperture decreases from the top of the gate stack to the bottom; Stress voltage, the stress voltage decreases with the decrease of the aperture of the channel part. The present invention applies multiple stress voltages between the gate stack and the polysilicon channel according to the actual shape of the channel hole when screening the electrical stress of the gate stack defect, and the stress voltage decreases with the decrease of the aperture of the channel hole. The small size makes the corresponding stress voltage of the large-sized storage region large, and the corresponding stress voltage of the small-sized storage region is small, so that the stress electric field of each storage layer is basically consistent.

Description

technical field [0001] The invention belongs to the field of semiconductor design, manufacture and testing, and in particular relates to a testing method and testing device for three-dimensional storage gate stack defects. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar flash memory and to pursue lower production costs per unit storage unit, a three-dimensional memory structure emerged as the times require. The three-dimensional memory structure can make each memory die in the memory device have more numbers. memory unit. [0003] In non-volatile memory, such as NAND memory, one way to increase memory density is by us...

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a testing method and testing device for three-dimensional memory gate stack defects, which are used to solve the problem of memory cell characteristic degradation or The problem that the stress voltage is too small to achieve the purpose of accelerating the failure of defects

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