Multiplier, data processing method, chip and electronic equipment

A multiplier and data technology, applied in the computer field, can solve the problem of large AI chip area and achieve the effect of reducing the area

Active Publication Date: 2020-06-09
SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, data with different bit widths needs to be multiplied by different multipliers, resulting in a large area occupied by the multiplier on the AI ​​chip.

Method used

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  • Multiplier, data processing method, chip and electronic equipment
  • Multiplier, data processing method, chip and electronic equipment
  • Multiplier, data processing method, chip and electronic equipment

Examples

Experimental program
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Embodiment Construction

[0076] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

[0077] The multiplier provided by this application can be applied to AI chips, field programmable gate array FPGA (Field-Programmable Gate Array, FPGA) chips, or other hardware circuit devices for multiplication processing. The specific structural diagram is as follows figure 1 and 2 shown.

[0078] like figure 1 as shown, figure 1 A structure diagram of a multiplier provided for an embodiment. like figure 1 As shown, the multiplier includes: a correction encoding circuit 11 and a correction compression circuit 12; the output end of the correction encoding circuit 11 ...

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Abstract

The invention provides a multiplier, a data processing method, a chip and electronic equipment. The multiplier comprises: a correction coding circuit and a correction compression circuit, the output end of the correction coding circuit is connected with the input end of the correction compression circuit, the multiplier can carry out multiplication operation on various data with different bit widths on the premise that the multiplication operation result accuracy is guaranteed, and the area of the AI chip occupied by the multiplier is effectively reduced.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a multiplier, a data processing method, a chip and electronic equipment. Background technique [0002] With the continuous development of digital electronic technology, the rapid development of various artificial intelligence (AI) chips has higher and higher requirements for high-performance digital multipliers. The neural network algorithm is one of the algorithms widely used in smart chips, and the multiplication operation through the multiplier is a common operation in the neural network algorithm. [0003] Usually, when multiplying data of different bit widths, data of the same bit width needs to be operated by an existing multiplier corresponding to the number of bits, and data of different bit widths needs to be operated by multiple existing multipliers of different bit widths. However, for data with different bit widths, different multipliers need to be used for multipl...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/523G06N20/00
CPCG06F7/523
Inventor 不公告发明人
Owner SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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