Parallel processing device and method for parallel multivalued reduction
A technology of parallel processing and equipment, applied in the direction of electrical digital data processing, processor architecture/configuration, multi-programming device, etc., which can solve problems such as computational difficulties, high throughput, and processing bottlenecks
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Embodiment 1
[0066] Embodiment 1 is a method for performing parallel M value reduction by a parallel processing unit of a parallel processing device, the method comprising:
[0067] Performing multiple initial reductions in series, each initial reduction operates on data in different corresponding register spaces of at least M register spaces;
[0068] moving data from the M register spaces such that all results from the plurality of initial reductions are in the same first register space; and
[0069] One or more subsequent reductions are performed in parallel to compute the M final values, each subsequent reduction operating only on data in said first register space.
Embodiment 2
[0070] Embodiment 2 is the method of embodiment 1, wherein the parallel processing device is a graphics processing unit.
Embodiment 3
[0071] Embodiment 3 is the method of any one of embodiments 1-2, further comprising: moving each result of the one or more subsequent reductions into a corresponding register of the same parallel processing unit.
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