Memory device and forming method thereof
A storage device and sacrificial layer technology, applied in semiconductor devices, electrical solid state devices, electrical components, etc., can solve the problems of NO stack structure damage, unsatisfactory performance of 3DNAND flash memory, etc.
Active Publication Date: 2020-07-24
YANGTZE MEMORY TECH CO LTD
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However, since the film properties of the ONO structure located at the lower end of the channel are similar to those of the NO stack structure, when the ONO structure is removed, the NO stack structure may also be damaged, which will make the formed 3D NAND flash memory performance is not as expected
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[0018] Reference will now be made in detail to the exemplary embodiments of the invention illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
[0019] Figure 1-2 A schematic diagram showing a semiconductor structure at certain stages in the fabrication process of a 3D NAND flash memory. refer to figure 1 , the first sacrificial layer 101 is formed on the base substrate 100 during the fabrication process of the 3D NAND flash memory. The first sacrificial layer 101 is made of polysilicon. Afterwards, a stacked structure formed of a plurality of interlayer dielectric layers 106 and a plurality of sacrificial layers 105 is formed on the first sacrificial layer 101 . The plurality of interlayer dielectric layers 106 and the plurality of sacrificial layers 105 are alternately arranged in a direction perpendicular to the surface of the base substrate 100 . The plurality ...
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Abstract
A method for forming a memory device includes: providing an initial semiconductor structure, the initial semiconductor structure including: a base substrate; a first sacrificial layer formed on the base substrate; a stack structure disposed on the first sacrificial layer; a plurality of channels formed through the stack structure and the first sacrificial layer; and a gate line trench formed through the stacked structure and exposing the first sacrificial layer. The method further comprises the following steps: forming at least one protective layer on sidewalls of the gate line trench; removing the first sacrificial layer using the at least one protective layer as an etch mask to expose portions of each of the plurality of trenches and a surface of the base substrate; and forming an epitaxial layer on the exposed surfaces of the base substrate and the plurality of trenches.
Description
technical field [0001] Generally speaking, the present disclosure relates to the technical field of semiconductor fabrication, and more specifically, the present disclosure relates to a memory device and a fabrication method thereof. Background technique [0002] With the development of planar flash memory, the manufacturing process of semiconductor electronic devices has made great progress. However, in recent years, the continuous development of planar flash memory has encountered many challenges, such as physical limitations, limitations of existing lithography techniques, and limitations of storage electron density. In this context, in order to solve the difficulties encountered by planar flash memory and pursue lower manufacturing costs per memory cell, various three-dimensional (3D) flash memory structures have emerged, including 3D or-not (NOR) and 3D And not (NAND). [0003] In a 3D flash memory with a NOR type structure, memory cells are arranged in parallel betwe...
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IPC IPC(8): H01L27/11517H01L27/11524H01L27/11563H01L27/1157H01L27/11578H01L27/11551
CPCH10B43/35H10B43/27H01L29/40117H10B43/40H10B41/20H10B41/35H10B41/46H10B43/20
Inventor 黄波薛磊薛家倩高庭庭耿万波刘小欣
Owner YANGTZE MEMORY TECH CO LTD