A dsp implementation method for suppressing inverter narrow pulse

Abstract

The invention discloses a DSP realization method for suppressing inverter narrow pulse. The duty cycle of the three-phase modulation wave is calculated by the DSP according to the real-time sampling voltage, current and other signals. The PWM module is used to update the PWM register, and output two complementary PWM signals with superimposed dead time, or the PWM module outputs one PWM signal to CPLD, the CPLD inverts the received PWM signal, superimposes dead zone time processing, and generates two complementary PWM signals with superimposed dead zone. Therefore, the DSP control method is used to suppress the narrow pulse, and solve the problem of IGBT loss and even damage to the bomber caused by the narrow pulse problem. The invention realizes minimum pulse width suppression based on DSP software control, solves the problems and deficiencies in the prior art, improves the safety and reliability of the IGBT, and thus improves the working performance of the entire inverter operation.

Description

technical field [0001] The invention relates to a DSP (Digital Signal Processor) implementation method for suppressing inverter narrow pulses, specifically an inverter narrow pulse suppression system and method for filtering out PWM (Pulse Width Modulation) pulses smaller than a fixed width through software control , belonging to the technical field of pulse width modulation. Background technique [0002] The inverter is one of the core units of photovoltaic power generation and energy storage systems. It uses power electronics technology to control power devices to achieve the purpose of electric energy conversion. With the increasing scale of photovoltaic power generation and energy storage systems, the system will Inverter performance requirements are getting higher and higher. The IGBT (Insulated Gate Bipolar Transistor) module is the key device of the inverter. The safety and reliability of its working performance are directly related to the reliability of the entire i...

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Problems solved by technology

[0004] 1. The use of CPLD (Complex Programmable Logic Device) to suppress narrow pulse signals requires more CPLD resources. If the CPLD resource capacity is not enough to filter out small pulse signals, a large-capacity CPLD chip needs to be replaced, which increases system costs;

[0005] 2. The DSP software forces the PWM module to output a 100% or 0% duty cycle when the duty cycle is less than or greater than the duty cycle corresponding to the minimum pulse width; because the PWM module is when the time base counter counts down to 0, it will take The duty cycle value is loaded to the comparison counter of the PWM module, so when the duty cycle is 100% or 0%, the output pulse width is half of the maximum pulse width of the two pulses in the preceding and following periods, and the output pulse width is still smaller than the minimum pulse width recommended by the manufacturer; DSP software is required to control and filter out the duty cycle value corresponding to twice the minimum pulse width, and the filter pulse width is large, which affects the performance of the inverter; and TI's C2000 series digital signal processor cannot output a duty cycle of 100% or 0%. Affects the implementation of software controls

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