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A data saturation plus package processing component, chip and device

A technology for digital processing chips and processing components, applied in digital data processing components, electrical digital data processing, instruments, etc., to achieve the effect of small number of adders, compact structure, and simple principle

Active Publication Date: 2022-06-03
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the existing implementation device for saturation plus packing operation completes saturation addition of a specific width, a group of adders of this specific width is usually required, and the result of the adder is subjected to saturation judgment before packing, which is only applicable to a specified The operation width of

Method used

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  • A data saturation plus package processing component, chip and device
  • A data saturation plus package processing component, chip and device
  • A data saturation plus package processing component, chip and device

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Embodiment Construction

[0030] As shown in FIG. 5, the first adder 501, the second adder 502, the third adder 503, and the fourth adder 504 are respectively

[0034] In addition, the present embodiment also provides a digital processing chip (DSP), which includes the aforementioned digital processing chip.

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Abstract

The invention discloses a data saturation plus packaging processing component, chip and equipment. The data saturation plus packaging processing component of the present invention includes a first adder, a second adder, a third adder, a fourth adder, and a multiplexer MUXA1~MUXA2, multiplexers MUXB1~MUXB2, multiplexers MUXC1~MUXC2, multiplexers MUXD1~MUXD4, first multiplexer, second multiplexer, third multiplexer, Four multiplexers. The present invention can perform saturation plus packing operation of two widths. The principle of the present invention is simple, and the structure is compact. Through the multiplexing of the adder and the multiplexer, the saturation plus packing operation of two different widths is realized. The required adder Fewer numbers make it widely applicable to digital signal processing systems where such operations need to be done.

Description

A data saturation plus packaging processing component, chip and device technical field The present invention relates to digital signal processing technology, be specifically related to a kind of data saturation plus packing processing component, chip and equipment. Background technique In the field of data signal processing, usually N / 2 bits or N bits of data are used to represent data, for example, 8 bits can be used To represent the brightness of a pixel, or use 16 bits to represent the color of a pixel. For these data, a series of operations. These operations may expand the data bit width. In order to maintain a certain calculation accuracy, it is necessary to perform The bit width of the intermediate result is preserved during the operation. However, in the final storage, it is still stored according to N / 2 bits or N bits, that is, to achieve Saturated addition operation. Taking the frequently used interpolation operation as an example, the pixel points A, ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/499G06F7/509
CPCG06F7/49921G06F7/509
Inventor 周理罗莉潘国腾张剑锋周海亮荀长庆铁俊波欧国东
Owner NAT UNIV OF DEFENSE TECH