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Coordination method for chip cutting errors in embedded micro-system module

A coordination method and chip technology, applied in the direction of microstructure technology, microstructure devices, etc., can solve the problems of reducing chip yield, chip damage, unbalanced wafer stress, etc., and achieve the effect of reducing production costs

Active Publication Date: 2020-09-22
浙江集迈科微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the laser cutting knife used in the first method is very expensive, so the first method cannot be popularized in a large area; the second method is relatively simple and common, but because the two back thinning processes (wet etching and chemical mechanical polishing) will affect the The chip is damaged (wet etching is easy to corrode to the functional area of ​​the chip because there is no etching reaction stop layer, and the method of chemical mechanical polishing is easy to cause stress on the wafer during the CMP process due to the unevenness of the chip on the front wafer during back polishing Cracked due to excessive imbalance) reduces the yield of chip production

Method used

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  • Coordination method for chip cutting errors in embedded micro-system module
  • Coordination method for chip cutting errors in embedded micro-system module
  • Coordination method for chip cutting errors in embedded micro-system module

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Embodiment Construction

[0036] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0037] like Figure 1 to Figure 18 As shown, a method for coordinating chip cutting errors in an embedded microsystem module specifically includes the following steps:

[0038] 101) Bare core preparation step: using a traditional mechanical dicing knife to cut the wafer to obtain figure 2 The single bare chip shown; due to the cutting progress of the dicing knife, there will be a large size error on the edge of the chip, and the chip error plane is as follows image 3 shown.

[0039] like Figure 4 As shown, the surface of the carrier plate is coated with an adhesive layer with a thickness of 5 microns to 100 microns; the coating method of the adhesive layer is spin coating, scraping glue or sticking a solid hard film; the adhesive used for the adhesive layer is a temporary bonding adhesive , Light degumming or thermal degumming can be deg...

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Abstract

The invention discloses a coordination method for chip cutting errors in an embedded micro-system module. The coordination method specifically comprises the following steps of 101) bare chip preparation, 102) bare chip correction and 103) preparation. The coordination method of the chip cutting errors in the embedded micro-system module is low in processing cost, reduces the damage possibility ofthe chip, and improves the reliability of a processing technology.

Description

technical field [0001] The patent of the present invention relates to the technical field of semiconductor packaging, more specifically, it relates to a method for coordinating chip cutting errors in embedded microsystem modules. Background technique [0002] With the development of silicon-based micro-electromechanical (MEMS) and radio-frequency through-silicon via (RF TSV) process technology, three-dimensional heterogeneous integrated microsystem technology has become an important direction for the development of next-generation military highly integrated electronic system technology. Three-dimensional heterogeneous integration is an integration method that embeds chips of different sizes and textures into the silicon cavities on the silicon-based substrate through post-wiring technology to fan out, and then through silicon vias to achieve high-density integration. [0003] However, such an integrated method of chip dicing and embedding has the problem of error matching be...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B81C99/00
CPCB81C99/001B81C99/0065
Inventor 郭西
Owner 浙江集迈科微电子有限公司