Neural network computing device and method and computing device

Abstract

The invention discloses neural network computing equipment, a neural network computing method and computing equipment, and belongs to the technical field of neural networks. According to the neural network computing device, a convolution kernel and input data to be subjected to convolution calculation are stored in a first storage array of a memory, a first computing circuit can read the convolution kernel and the input data to be subjected to convolution calculation from the first storage array, and convolution calculation is completed. According to the invention, neural network calculation is realized in the memory, transmission of neural network data between the memory and the neural network calculation nodes is reduced, and the problem of a memory wall is solved.

Description

technical field [0001] The invention relates to the technical field of neural networks, in particular to a neural network computing device, method and computing device. Background technique [0002] With the development of convolutional neural networks, image recognition and speech recognition can be performed through convolutional neural network calculations. Since convolutional neural network calculations are highly parallel and data-intensive calculations, when the processor of the computing device uses Feng When the Neumann computing architecture performs convolutional neural network calculations, the processor will first store the data of the convolutional neural network into the memory. Usually, the memory is a dynamic random access memory (DRAM). Then, the data bus transfers the data stored in the DRAM to the neural network computing node, and the convolutional neural network calculation is completed in the neural network computing node. After the calculation is comp...

AI Technical Summary

Problems solved by technology

Due to the huge amount of data and complex calculations of the convolutional neural network, the data bus needs to transmit data back and forth between the DRAM and the neural network computing nodes. When the processor operating frequency is required to be high, the bandwidth of the data bus connecting the processor and the DRAM will be insufficient. In order to transmit the data required by the processor, the problem of the memory wall will easily appear

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