DRAM memory timing configuration method and device

Abstract

The invention discloses a DRAM memory sequence configuration method and device, wherein the method includes the following steps: writing first data at a preset position of the DRAM memory; enabling the TDQS function of the DRAM memory; Write the second data bit, the bit data of the second data is different from the bit data of the first data; close the TDQS function of the DRAM memory; read the data from the preset position of the DRAM memory, and judge whether the read data is equal to the second data; if it is equal to the second data, the recognition result of the DRAM memory is the first DRAM; if it is not equal to the second data, the recognition result of the DRAM memory is the second DRAM; according to the recognition result and the pre-stored timing table to obtain the corresponding timing, The timing table stores the timing corresponding to the first DRAM and the timing corresponding to the second DRAM; and configures the corresponding timing to the DRAM memory. The present invention can identify memory particles with different line widths, can configure corresponding timing, and improves memory efficiency.

Description

technical field [0001] The invention relates to the field of timing configuration of DRAM memory, in particular to a method and device for timing configuration of DRAM memory. Background technique [0002] For embedded systems in the industry, such as figure 1 and figure 2 The system includes the main control chip SOC (system-on-chip) and DRAM (dynamic random access memory) memory. The memory line width is also 32-bit line width, and the same is the total DDR capacity of 2GB (16Gb). The existing technology can have such 2 hardware implementation methods (x4bit is generally not considered, because there are many memory particles and the board area is large). Although these two methods are available, there is a difference in the timing of tRFC (row address refresh cycle) between memory particles with a capacity of 8Gb (line width x16bit) and memory particles with a capacity of 4Gb (line width x8bit). [0003] For example: the relationship between tRFC and capacity of DDR3 ...

AI Technical Summary

Problems solved by technology

[0011] Therefore, it is necessary to provide a DRAM memory timing configuration method and device to solve the problems of unrecognizable memory particle types and low bandwidth utilization in the existing various memory hardware solutions

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