Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Implementation method of NVMe solid-state storage system and architecture

A technology of solid-state storage and implementation method, which is applied in the direction of instrumentation, electrical digital data processing, etc., can solve the problems of no public and general version, achieve the effect of breaking through the bottleneck of speed transmission, improving data transmission bandwidth and parallel processing ability of instructions

Active Publication Date: 2021-01-01
SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD
View PDF7 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, at present, there is no public and general version of NVMe solid-state storage system design, which is often independently developed by solid-state disk manufacturers and controlled by a few top solid-state storage manufacturers.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Implementation method of NVMe solid-state storage system and architecture

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0052] Reference attached figure 1 , the present embodiment proposes an implementation method of an NVMe solid-state storage system. On the basis of the ARM processor and the Avalon bus, the Avalon bus includes the Avalon-MM bus and the Avalon-ST bus;

[0053] Based on the PCIe interface protocol, customize and configure the PCIe IP core, so that the host can discover the corresponding PCIe device, and realize the data communication function between the host and the device;

[0054] Based on the NVMe protocol, customize FPGA NVMe IP core and NVMe IP core storage data structure, ARM processor connects NVMe IP core and NVMe IP core storage data structure through Avalon-MM bus, NVMe IP core connects PCIe IP through Avalon-ST bus nuclear;

[0055] Customize and configure the EMIF IP core. The ARM processor is connected to the EMIF IP core through the Avalon-MM bus. One end of the EMIF IP core is connected to the NVMe IP core of the FPGA through the Avalon-MM bus to complete the r...

Embodiment 2

[0067] Reference attached figure 1 , this embodiment proposes an implementation architecture of an NVMe solid-state storage system, which includes an ARM processor, an Avalon bus, a PCIe IP core, an NVMe IP core and an NVMe IP core storage data structure, an EMIF IP core, DDR4 SDRAM, and a NAND Flash Controller IP Core and NAND Flash.

[0068] Avalon bus includes Avalon-MM bus and Avalon-ST bus.

[0069] The ARM processor is connected to the NVMe IP core and NVMe IP core storage data structure, EMIF IP core, and NAND Flash Controller IP core through the Avalon-MM bus.

[0070] The NVMe IP core is connected to the PCIe IP core through the Avalon-ST bus to complete the read and write control from the PCIe IP core to the NVMe IP core.

[0071] One end of the EMIF IP core is connected to the NVMe IP core of the FPGA through the Avalon-MM bus to complete the read and write control from the NVMe IP core to the EMIFIP core. The other end of the EMIF IP core is connected to the DDR4...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an implementation method of an NVMe solid-state storage system, relates to the technical field of storage equipment, and aims to customize and configure a PCIe IP core based ona PCIe interface protocol, so that a host end can discover corresponding PCIe equipment. Based on an NVMe protocol, an NVMe IP core of the FPGA and an NVMe IP core storage data structure are customized, and the NVMe IP core is connected with a PCIe IP core; an EMIF IP core is customized and configured, the EMIF IP core is connected with the NVMe IP core and the DDR4 SDRAM, PCIe IP core data is read, and the PCIe IP core data is cached in the DDR4 SDRAM; and the method also includes customizing and configuring an NAND Flash Control IP (Internet Protocol) core and an NAND Flash, wherein the NAND Flash Control IP core reads cache data of the DDR4 SDRAM and transmits the cache data to the NAND Flash. The invention further discloses an implementation architecture which is combined with the method to complete writing and reading of the data.

Description

technical field [0001] The invention relates to the technical field of storage devices, in particular to an implementation method and architecture of an NVMe solid-state storage system. Background technique [0002] Since entering the information age in the 21st century, the information explosion has followed, and the ever-increasing amount of information has put forward higher requirements for storage devices. [0003] Hard drives include solid state drives (Solid State Drive, referred to as SSD, new hard drives, also known as solid-state storage systems), mechanical hard drives (HDD, traditional hard drives), and hybrid hard drives (HHD, a new hard drive based on traditional mechanical hard drives). SSD uses flash memory particles for storage, HDD uses magnetic discs for storage, and hybrid hard disk (HHD: Hybrid Hard Disk) is a hard disk that integrates magnetic hard disk and flash memory. [0004] A solid-state storage system is a hard disk made of a solid-state electro...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F13/16
CPCG06F13/1684G06F2213/0026
Inventor 宋琦陈乃阔吴之光
Owner SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products