Implementation method of NVMe solid-state storage system and architecture
A technology of solid-state storage and implementation method, which is applied in the direction of instrumentation, electrical digital data processing, etc., can solve the problems of no public and general version, achieve the effect of breaking through the bottleneck of speed transmission, improving data transmission bandwidth and parallel processing ability of instructions
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Embodiment 1
[0052] Reference attached figure 1 , the present embodiment proposes an implementation method of an NVMe solid-state storage system. On the basis of the ARM processor and the Avalon bus, the Avalon bus includes the Avalon-MM bus and the Avalon-ST bus;
[0053] Based on the PCIe interface protocol, customize and configure the PCIe IP core, so that the host can discover the corresponding PCIe device, and realize the data communication function between the host and the device;
[0054] Based on the NVMe protocol, customize FPGA NVMe IP core and NVMe IP core storage data structure, ARM processor connects NVMe IP core and NVMe IP core storage data structure through Avalon-MM bus, NVMe IP core connects PCIe IP through Avalon-ST bus nuclear;
[0055] Customize and configure the EMIF IP core. The ARM processor is connected to the EMIF IP core through the Avalon-MM bus. One end of the EMIF IP core is connected to the NVMe IP core of the FPGA through the Avalon-MM bus to complete the r...
Embodiment 2
[0067] Reference attached figure 1 , this embodiment proposes an implementation architecture of an NVMe solid-state storage system, which includes an ARM processor, an Avalon bus, a PCIe IP core, an NVMe IP core and an NVMe IP core storage data structure, an EMIF IP core, DDR4 SDRAM, and a NAND Flash Controller IP Core and NAND Flash.
[0068] Avalon bus includes Avalon-MM bus and Avalon-ST bus.
[0069] The ARM processor is connected to the NVMe IP core and NVMe IP core storage data structure, EMIF IP core, and NAND Flash Controller IP core through the Avalon-MM bus.
[0070] The NVMe IP core is connected to the PCIe IP core through the Avalon-ST bus to complete the read and write control from the PCIe IP core to the NVMe IP core.
[0071] One end of the EMIF IP core is connected to the NVMe IP core of the FPGA through the Avalon-MM bus to complete the read and write control from the NVMe IP core to the EMIFIP core. The other end of the EMIF IP core is connected to the DDR4...
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