A dbbc synchronous acquisition time delay control method

Abstract

The present invention provides a DBBC synchronous acquisition time delay control method, which considers the time delay consistency problem of different power-on, can realize the high stability control of synchronous acquisition time delay, and does not need to re-calibrate after each power-on , which solves the problem that the zero value of the device restart delay is uncertain. The present invention designs the synchronous starting mechanism of CLK, ADC and FPGA data processing, and adopts a synchronous trigger control strategy based on 1PPS to ensure that τ syn_ADC , τ syn_clk and τ syn_FPGA It remains stable every time it is turned on, which solves the problem of uncertain zero value of the device restart delay. The measured data shows that the system delay stability is better than 0.01ns, and the high stability control of the device start-up delay is realized. , after each start-up, there is no need to re-calibrate, thus greatly improving the efficiency of VLBI observation.

Description

technical field [0001] The invention relates to the technical field of radio astronomy, in particular to a DBBC synchronous acquisition delay control method. Background technique [0002] Based on the principle of interferometry technology (the block diagram of the interferometry system is shown in figure 1 As shown), it can be seen that the system delay of DBBC (DigitalBase Band Converter, baseband conversion and recording system) is used as VLBI (Very Long Baseline Interferometer, very long baseline interferometer, VLBI system composition and measurement principle are as follows figure 2 Shown) part of the geometric delay measurement error needs to be calibrated and eliminated during observation. In the case of constant working environment and temperature, the DBBC system delay can be divided into two parts: fixed delay and synchronous acquisition delay from the perspective of whether the delay changes: ① The fixed delay refers to the Fixed delay, including cable delay ...

AI Technical Summary

Problems solved by technology

However, since the clock, ADC and FPGA are not synchronized, the synchronous acquisition delay of DBBC relative to 1PPS will be inconsistent every time it is turned on, which will cause the following problems:

[0014] 1. Every time the DBBC is turned on, it must use radio sources and other means to perform time delay calibration. If there is no suitable radio source for observation, the synchronization acquisition error cannot be completely eliminated;

[0015] 2. After the DBBC delay is calibrated, if there are abnormal situations such as power failure and crash, it needs to be calibrated again after starting up, which will take up valuable observation time;

[0016] 3. It is not conducive to discovering abnormal delay changes

[0017] It can be seen that similar devices at home and abroad only consider the problem of the delay consistency of synchronous acquisition after one boot, but do not consider the delay consistency of different boots, resulting in the need to re-calibrate after each boot, reducing the VLBI observation efficiency, unable to achieve high stability control of synchronous acquisition delay

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