Integrated circuit clock tree network quality assessment method, device and medium

Abstract

The invention discloses an integrated circuit clock tree network quality evaluation method, device and storage medium, belonging to the integrated circuit design industry. The method includes: building and adjusting a clock tree network in an EDA tool, and obtaining an uncertain optimal clock tree network through the convergence of a heuristic algorithm; after performing at least one experiment on the uncertain optimal clock tree network, it is found that the uncertain optimal clock tree network The number of times that the tree network still has optimization potential; according to the number of times that the uncertain optimal clock tree network still has optimization potential and the probability that the uncertain optimal clock tree network still has optimization potential, the uncertain optimal clock is calculated using the binomial distribution formula Probability of acceptable quality for tree networks. Among them, the probability that the uncertain optimal clock tree network has optimization potential is obtained through a large number of experiments in the early stage or is artificially set. The application of the present invention breaks away from human judgment and realizes automatic quantitative evaluation. Constrain and judge whether the clock tree network is accepted or not in a probabilistic way.

Description

technical field [0001] The present application relates to the technical field of integrated circuit design, in particular to a method, system, storage medium and equipment for evaluating the quality of an integrated circuit clock tree network. Background technique [0002] The basis of digital integrated circuit design methodology is the register transfer model. The integrated circuit described in this way relies on registers at various levels to store and process data streams. If these registers want to work together, they must be under the command of one or more clock beats. Then, for digital integrated circuits designed on wafers, solving the architectural problem of effective clock propagation becomes one of the key issues in physical implementation. [0003] At present, the most mature clock network structure is the tree structure. The tree structure can generate branches anywhere. In theory, it can always grow new branches at the most suitable place. There is no abso...

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Problems solved by technology

[0005] The integrated circuit clock tree network quality evaluation method solves the problem that integrated circuit design engineers need to judge the quality of clock tree network through experience and need to introduce multiple variables in the evaluation process

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