Optimized data rearrangement method based on base-64 two-dimensional FFT architecture

A 64FFT, data optimization technology, applied in the field of signal processing, can solve the problems of less FFT output rearrangement technology, less mature technology, multiple clock cycles, etc., to reduce the number of operation execution cycles and efficient output reordering technology Effect

Pending Publication Date: 2021-02-05
HOHAI UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0021] At present, there are few researches on FFT output rearrangement technology and its complexity, and no more mature technology has appeared
On most existing architectures, reordering requires dedicated hardware or large amounts of memory
and require more clock cycles to execute

Method used

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  • Optimized data rearrangement method based on base-64 two-dimensional FFT architecture
  • Optimized data rearrangement method based on base-64 two-dimensional FFT architecture
  • Optimized data rearrangement method based on base-64 two-dimensional FFT architecture

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Embodiment

[0063] Such as figure 1 Shown is the parallel unroll architecture of base-64 blocks. There are 16 base 4 units in the first stage, 4 base 4 units in the second stage, and 1 base 4 unit in the third stage. In this architecture, all base 4 blocks are the same. Symbols R40, R44, R48, R412 represent the 0th, 4th, 8th, 1st two radix-4 butterfly blocks and so on. W16 and W64 represent the twiddle factors for the first and second stages. The first stage has 16 twiddle factors and uses read-only memories (ROMs) to store W16. Each ROM contains four twiddle factor values. The second stage consists of four base 4 cells and four ROMs for storing W64. Each ROMs in the second stage consists of 16 twiddle factor values.

[0064] Among the N multipliers in each stage, the first N / 4 multipliers in each stage have the same twiddle factor. So at execution time, these multipliers are removed. Therefore, the first stage has 1 two multipliers instead of 16, and the second stage has 3 multip...

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Abstract

The invention discloses an optimized data rearrangement method of a two-dimensional FFT architecture based on a base 64, belongs to the technical field of signal processing, and provides a new two-dimensional FFT architecture by utilizing an effective data rearrangement technology and using a base 64 algorithm. According to the architecture, two parallel expansion base 64 blocks are cascaded to develop a 64 * 64 two-dimensional FFT architecture. In a base-64 structure, data rearrangement is performed using a six-bit mode selection signal as a control signal. According to the base-64 structureprovided by the invention, an intermediate memory is remarkably reduced in a one-dimensional FFT, and the delay is reduced; and according to the proposed two-dimensional FFT structure, the number of intermediate memories between two one-dimensional FFTs is reduced from N2 to N; the method has high flexibility, can be applied to multiple occasions, and is especially suitable for data reconstructionof an original image.

Description

technical field [0001] The invention belongs to the technical field of signal processing, and in particular relates to an optimized data rearrangement method based on a base-64 two-dimensional FFT architecture. Background technique [0002] The past few decades have seen an explosion of research and applications in the field of signal processing. Digital signal processing (DSP) has a wide range of applications in biomedical imaging, multimedia, digital television, broadcasting and other fields. The realization of these applications has become possible due to the development of very large scale integration (VLSI) technology. Developing hardware solutions for these applications has been an active area of ​​research over the past two decades. [0003] Discrete Fourier Transform (DFT) is an important part of DSP and communication systems. The Fast Fourier Transform (FFT) is the most commonly used fast method for computing the discrete Fourier transform. Two-dimensional FFTs ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/14
CPCG06F17/142
Inventor 曹宁吴子诚冯晔
Owner HOHAI UNIV
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