Unlock instant, AI-driven research and patent intelligence for your innovation.

A programmable parser and its parsing method under multi-level parallel high-speed processing

A high-speed processing and resolver technology, applied in the field of IP communication, can solve the problems of low efficiency and achieve the effect of improving the resolution rate

Active Publication Date: 2022-04-01
FENGHUO COMM SCI & TECH CO LTD +1
View PDF17 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The NPU architecture in the industry also encounters the problem of low efficiency when processing short packet applications

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A programmable parser and its parsing method under multi-level parallel high-speed processing
  • A programmable parser and its parsing method under multi-level parallel high-speed processing
  • A programmable parser and its parsing method under multi-level parallel high-speed processing

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0063] Embodiment 1 of the present invention provides a programmable parser under multi-level parallel high-speed processing, such as figure 1 As shown, it includes a first-level distribution balance module, a cell analysis engine, and a first-level sort management module, wherein each cell analysis engine also includes a second-level distribution balance module and a second-level sort management module, specifically:

[0064] The first-level distribution and balancing module is used to balance the traffic between the cell parsing engines, and distribute the obtained data packets to each cell parsing engine for parsing according to load balancing;

[0065] Such as figure 2 As shown, it shows an example of a distribution process of the first-level distribution and equalization module. Each clock cycle, the first-level distribution and equalization module collects signals from the matching engine (that is, the loc_Eng state is idle / busy) in each cell analysis engine to obtain ...

Embodiment 2

[0110] The embodiment of the present invention also provides an analysis method of a programmable parser under multi-stage parallel high-speed processing. As a common inventive concept, the analysis method can be applied to run in the programmable parser described in Embodiment 1. In addition, the expansion and details of the technical solution carried out in Embodiment 1 are also applicable to the embodiment of the present invention, wherein, in consideration of the content of the description, the corresponding extended content in Embodiment 1 will not be implemented in the present invention The examples are repeated.

[0111] In the parsing method of the embodiment of the present invention, each received data packet to be parsed will be assigned a number pkt_id, such as Figure 4 As shown, the parsing methods include:

[0112] In step 201, when a data packet is analyzed to generate a packet header vector PHV, the number pkt_id inherited from the packet by the packet header ...

Embodiment 3

[0140] Such as Figure 5 As shown, it is a schematic diagram of the architecture of the programmable analysis device under the multi-stage parallel high-speed processing of the embodiment of the present invention. The programmable analysis device under multi-level parallel high-speed processing in this embodiment includes one or more processors 21 and memory 22 . in, Figure 5 A processor 21 is taken as an example.

[0141] Processor 21 and memory 22 can be connected by bus or other means, Figure 5 Take connection via bus as an example.

[0142] Memory 22, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs and non-volatile computer-executable programs, such as programmable analysis under multi-level parallel high-speed processing in Embodiment 1 method. The processor 21 executes the programmable analysis method under multi-level parallel high-speed processing by running the non-volatile software programs and instructio...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to the technical field of IP communication, and provides a programmable parser under multi-stage parallel high-speed processing and a parsing method thereof. The parser balances the traffic between the cell parsing engines, and distributes the obtained data packets to each cell parsing engine according to the load balance for parsing; according to the time slots of the state jumps of multiple parallel matching engines, the data packet parsing task is performed Assigning; extracting the matching information of the field contained in the protocol header to be parsed from the data packet header, parsing out the corresponding field of the protocol header to be parsed and writing it into the packet header vector; interacting with the secondary sorting management module to manage multiple cell parsing engines The packet output selection of the parsed packet header vector. The present invention implements parallel processing to improve the overall analysis rate through multiple cell analysis engines associated with the first-level distribution balance module, and multiple matching engines associated with TCAM and SRAM in each cell analysis engine.

Description

【Technical field】 [0001] The invention relates to the technical field of IP communication, in particular to a programmable parser under multi-level parallel high-speed processing and a parsing method thereof. 【Background technique】 [0002] The packet parser of the switch forwarding engine is to analyze the header of the network protocol message. It takes the data frame header from the forwarding engine and the corresponding port information, storage address and other description information (descriptor) as input data, and these data The key fields in the search engine are parsed, identified and extracted to be output to subsequent search engines in the forwarding engine. In the actual packet parser module, in addition to parsing the message header and extracting fields, it will also carry the original input descriptor and follow the message along the pipeline to the subsequent stage, but it will not participate in the extraction process. [0003] Software Defined Network (...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F8/30G06F8/41G06F9/48G06F9/50
CPCG06F8/37G06F8/427G06F8/4452G06F9/4881G06F9/505G06F2209/484
Inventor 唐棣鲁鹏唐文龙张伟刘永冲鄢文飞
Owner FENGHUO COMM SCI & TECH CO LTD