Method and device for iterative calculation parallel granule division of integrated circuit interlayer coupling
An integrated circuit and iterative computing technology, applied in CAD circuit design, complex mathematical operations, design optimization/simulation, etc., to avoid hard disk read and write bottlenecks and reduce waiting time
Active Publication Date: 2021-07-13
北京智芯仿真科技有限公司
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Problems solved by technology
In order to minimize the communication between processes in the iterative calculation process of multi-layer VLSI layer coupling, avoid the hard disk read and write bottleneck caused by the peak value of memory being greater than the available physical memory during multi-process parallel computing, and perfect To solve the process waiting problem caused by the unequal complexity of different computing instances, and thus greatly improve the efficiency of parallel computing, this application discloses the following technical solutions
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[0042] In order to make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be described in more detail below in conjunction with the drawings in the embodiments of the present invention.
[0043] It should be noted that: in the drawings, the same or similar symbols represent the same or similar elements or elements with the same or similar functions. The described embodiments are part of the embodiments of the present invention, but not all of the embodiments. In the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
[0044] In describing the present invention, it is to be understood that...
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The present invention provides a method and device for dividing iterative calculation parallel particles of integrated circuit interlayer coupling. First, iterative calculation is divided into three types of calculation units: basic calculation unit, integrated circuit layer-layer calculation unit and electromagnetic field and current distribution of each layer computing unit; secondly, according to the three types of computing units, the iterative calculation of interlayer coupling of the integrated circuit is divided into non-overlapping computing particles; thirdly, based on a complete serial iterative computing, the weighted CPU time sum of each computing particle is obtained For the total CPU time, the calculation granules are merged into different parallel granules according to the proportion of the weighted CPU time; finally, the parallel granules are classified, and the parallel granules of the same kind are independent of each other, and the corresponding calculation task sequences can be randomly disrupted. Form a new computing task sequence and dynamically assign it to different computing processes. The invention determines a high-efficiency parallel computing parallel particle division method for the inter-layer coupling calculation of the integrated circuit, and reduces the simulation time of the integrated circuit.
Description
technical field [0001] The invention relates to the technical field of iterative calculation of interlayer coupling of integrated circuits, in particular to a method and device for dividing parallel particles of iterative calculation of interlayer coupling of integrated circuits. Background technique [0002] When the integrated circuit is working, due to the transmission of high-speed signals on its multi-layer layout, a high-frequency alternating electromagnetic field will be formed. These high-frequency alternating electromagnetic fields will form a high-frequency radiation source, causing crosstalk to other signal layers or other integrated circuits and chips. and electromagnetic radiation, affecting the normal operation of other signal layers or other integrated circuits and chips, so when designing, it is necessary to calculate the influence of space electromagnetic radiation between the various layers of the integrated circuit. In the traditional calculation of the sp...
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IPC IPC(8): G06F30/23G06F30/33G06F17/16G06F17/18
CPCG06F17/16G06F17/18G06F30/23G06F30/33
Inventor 唐章宏邹军王芬黄承清汲亚飞
Owner 北京智芯仿真科技有限公司