Coarse-grained parallel iterative method and device for inter-layer coupled partial accumulation of integrated circuits

Abstract

The present invention provides a coarse-grained parallel iterative method and device for accumulating interlayer coupling of integrated circuits. The parallel iterative method is as follows: first, the calculation of interlayer coupling of integrated circuits is divided into two types of parallel coarse-grained, the first type is based on two-dimensional The finite element calculation of the electromagnetic field and current distribution of each layer of the integrated circuit, the second type is based on the dyadic Green's function to calculate the influence of the source layer on other layers; secondly, establish a management process to control the entire iterative cycle, and divide each iteration based on parallel coarse particles The calculation is divided into multiple calculation tasks, and multiple calculation processes are initiated in parallel, and the calculation tasks are dynamically distributed to each calculation process. Each calculation process independently completes the calculation tasks, and updates the electromagnetic field and current distribution of each source layer of the integrated circuit through repeated iterations. , and the scope of action of each source layer, until the changes of all fields are less than the specified threshold, the iteration ends. The application can make the calculation time of the electromagnetic response of the three-dimensional multilayer integrated circuit decrease linearly with the number of parallel processes.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a coarse-grained parallel iterative method and device for inter-layer coupling partial accumulation of integrated circuits. Background technique [0002] When the integrated circuit is working, due to the transmission of high-speed signals on its multi-layer layout, a high-frequency alternating electromagnetic field will be formed. on a small semiconductor substrate. In order to achieve more functions, VLSI has dozens to hundreds of layers of structure, each layer structure is extremely complex, integrating millions or even tens of millions of transistors, and has a multi-scale structure, from the centimeter level to the latest state-of-the-art nanoscale. In order to ensure that the integrated circuit can work normally and realize the functions designed in advance, it is necessary to ensure the power integrity and signal integrity of the integrated circuit first. A...

AI Technical Summary

Problems solved by technology

[0005] Based on the above problems, the present invention proposes a coarse-grained parallel iterative method and device for accumulating interlayer coupling parts of integrated circuits. Avoid the hard disk reading and writing bottleneck caused by the peak value of the memory being greater than the available physical memory during multi-process parallel computing, and at the same time perfectly solve the process waiting problem caused by the unequal complexity of different computing instances, thereby greatly improving the efficiency of parallel computing. This application discloses the following Technical solutions

Images