Intelligent chip architecture and method for efficiently processing data

An intelligent chip and data technology, applied in the computer field, can solve problems such as inability to apply concurrent transmission and processing of large amounts of data, inability to transmit data in a timely manner, inability to implement single-cycle instructions, etc., to improve data processing efficiency, reduce bus congestion, The effect of increasing throughput

Active Publication Date: 2021-10-15
河南亿秒电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when it is necessary to write data back to memory or access memory data, the pipeline needs to be interrupted or waited, which is essentially impossible to achieve single-cycle instructions or higher execution efficiency
However, this type of architecture cannot be applied to concurrent transmission and processing of large amounts of data
[0007] In addition, due to the design of the bus bandwidth, such as large data access from peripherals to memory, memory to memory, memory to peripherals, or DMA (Direct Memory Access, direct memory access)) transmission, often requires the bus president Allocation is performed to prevent the DMA from taking too long to cause the CPU to wait idle, or the CPU to occupy the bus for a long time, so that the peripheral data cannot be transmitted to the memory in time and the data is overwritten by new data. In order to solve this problem, the existing technology uses increased The length of the pipeline is used to improve the execution efficiency of instructions, but the longer the pipeline, the more complex the design of the chip architecture, and the easier it is to cause pipeline deadlock, which requires forced waiting or clearing the pipeline, and re-establishing the pipeline consumes a certain number of clock cycles. If the pipeline is frequently cleared and established, the execution efficiency of the chip will decrease instead.

Method used

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  • Intelligent chip architecture and method for efficiently processing data
  • Intelligent chip architecture and method for efficiently processing data

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0046] Such as Figure 1-2 As shown, in the first aspect, a smart chip architecture of the present invention includes: an analog-to-digital unit ADC, an integer-to-floating-point unit UI2F, a floating-point unit FPU, a storage unit, an arithmetic logic unit ALU, and a data transmission control unit DTC And the bus array control unit BCC;

[0047] The analog-to-digital unit ADC is connected to the integer-to-floating-point unit UI2F;

[0048] Among them, it should be noted that the analog-to-digital unit ADC is used to convert analog quantities to digital quantities, thereby converting data into unsigned integer data that can be recognized by the processor; generally speaking, the analog-to-digital unit The number of bits converted by the ADC is 8 to 24 bits. According to different application fields, the requirements for the number of bits are also different. Generally, MCUs are configured with a data width of 12 bits, but in the audio field, it may be configured to 24 bits t...

Embodiment approach

[0075] As an optional implementation, the bus array control unit BCC is used for:

[0076] receiving the first control signal, and switching between data buses and / or address buses according to the first control signal.

[0077] Specifically, the bus array control unit BCC receives the first control signal sent by the data transmission control unit DTC through the DBCH bridge control bus, and implements the above-mentioned data bus (HDB, SDB, UFBB) according to the first control signal , UFBA, DBA, DBB, FBA, FBB, FOB, DBDA and DBDB) and the above-mentioned address bus (HAB, SAB, ABDA and ABDB), so as to realize the switching between the buses, and then realize the switching of data Multidirectional transmission.

[0078] As an optional implementation, the bus array control unit BCC includes transmission gates or tri-state bus buffers; wherein, the above-mentioned data buses and address buses can control the transmission gates or tri-state bus buffers of the BCC through the bu...

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Abstract

The invention discloses an intelligent chip architecture, which comprises an analog-to-digital unit, an integer-to-floating-point unit, a floating-point arithmetic unit, a storage unit, an arithmetic logic unit, a data transmission control unit and a bus array control unit. The analog-to-digital unit is connected with the integer-to-floating-point unit; the integer-to-floating-point unit is connected with the bus array control unit and is connected with the data transmission control unit; the floating-point arithmetic unit is connected with the bus array control unit; a storage unit is connected with the bus array control unit and the data transmission control unit; the arithmetic logic unit is connected with the data transmission control unit; and the data transmission control unit is also connected with the bus array control unit. According to the method, the waiting period of the bus is shortened, the bus congestion is reduced, and the data processing throughput and the data processing efficiency are improved; and the mode of double data buses and double address buses can effectively reduce the pipeline length of the intelligent chip architecture, simplify the architecture design and shorten the consumed clock cycle.

Description

technical field [0001] The invention belongs to the technical field of computers, and in particular relates to an intelligent chip architecture and a method for efficiently processing data. Background technique [0002] MCU (Microcontroller Unit, micro control unit), also referred to as μC, or called a single chip processor architecture (Single Chip Microcontroller), by combining ROM (Read-Only Memory, read-only memory), RAM (Random Access Memory, Random access memory), CPU (central processing unit, central processing unit), I / O (Input / Output, input and output interface) are integrated in the same chip, and different combinations are controlled for different applications to form different intelligence chip architecture. The existing smart chip architecture mainly has the following defects: [0003] (1) In digital signal processing, in order to ensure the accuracy of calculations or the convergence of algorithms, floating-point operations are often required; and with the de...

Claims

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Application Information

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IPC IPC(8): G06F7/57G06F13/28
CPCG06F7/57G06F13/28Y02D10/00
Inventor宋大为
Owner河南亿秒电子科技有限公司