A Coarse-grained Reconfigurable Array Parallel Instruction Configuration Device and Processor
A configuration device, coarse-grained technology, applied in concurrent instruction execution, machine execution device, electrical digital data processing and other directions, can solve problems such as unacceptable circuit complexity, and achieve the goal of improving instruction transmission speed, reducing the number, and reducing hardware costs. Effect
Active Publication Date: 2022-06-07
江苏清微智能科技有限公司
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For larger N and M, the circuit complexity can be considered unacceptable
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[0035] In order to make the objectives, technical solutions and advantages of the present invention clearer and more comprehensible, the present invention will be further described below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
[0036] figure 1 It is a block diagram of a coarse-grained reconfigurable array parallel instruction configuration apparatus according to an embodiment of the present invention, the apparatus includes an instruction issuing unit 1, a processing unit 3, a switching network 2 and a path control unit 4; the switching network 2 adopts a butterfly structure , be provided with n input ports and n output ports, the N outp...
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The invention provides a coarse-grained reconfigurable array parallel instruction configuration device and a processor. The device includes an instruction issuing unit, a processing unit, a switching network and a path control unit; the switching network adopts a butterfly structure, and is provided with n input ports and n output ports, and the N output ports of the instruction issuing unit are connected to the switching network respectively. The M processing units are respectively connected to an output port of the switching network; the path control unit outputs the corresponding control code to the switching network to connect the n input ports and n output ports one by one, so that The instructions sent by the instruction issuing unit from its output port are transmitted to the processing unit in parallel through the switching network. The invention can realize the parallel transmission of instructions and improve the instruction transmission speed; compared with the crossbar structure, both the number of connections and the number of switching units are greatly reduced, and the hardware cost is reduced.
Description
technical field [0001] The present invention relates to the technical field of processors, and in particular, to an apparatus and method for configuring instructions of a processing unit. Background technique [0002] In 1999, Dehon and Wawrzynel of the Reconfigurable Technology Research Center at the University of California, Berkeley, defined reconfigurable computing as a computing organization with the following characteristics: First, after its manufacture, the function of the chip can still be customized to solve any problem; The second is to achieve a large degree of spatial mapping from tasks to chips to complete calculations. Any computing method that satisfies the above characteristics can be called reconfigurable computing. The first feature states that reconfigurable computing is programmable after production, so it has flexibility similar to general-purpose processors; the second feature states that reconfigurable computing uses spatially parallel computing meth...
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IPC IPC(8): G06F9/38G06F15/173
CPCG06F9/3836G06F15/17312Y02D10/00
Inventor 黄鑫唐士斌欧阳鹏
Owner 江苏清微智能科技有限公司