Coarse-grained reconfigurable array parallel instruction configuration device and processor

Abstract

The invention provides a coarse-grained reconfigurable array parallel instruction configuration device and a processor. The device comprises an instruction issuing unit, a processing unit, a switching network and a path control unit, the switching network adopts a butterfly structure and is provided with n input ports and n output ports, the N output ports of the instruction issuing unit are respectively connected with one input port of the switching network, and the M processing units are respectively connected with one output port of the switching network; the path control unit outputs corresponding control codes to the switching network to enable the n input ports and the n output ports to be communicated in a one-to-one correspondence mode, and therefore instructions sent by the instruction issuing unit from the output ports are transmitted to the processing unit in parallel through the switching network. Parallel transmission of instructions can be achieved, and the instruction transmission speed is increased; compared with a crossbar structure, the number of connecting wires and the number of switching units are greatly reduced, and the hardware cost is reduced.

Description

technical field [0001] The present invention relates to the technical field of processors, in particular to a device and method for instruction configuration of a processing unit. Background technique [0002] In 1999, Dehon and Wawrzynel of the Reconfigurable Technology Research Center of the University of California, Berkeley defined reconfigurable computing as a computing organizational structure with the following characteristics: First, after its manufacture, the function of the chip can still be customized to solve any problem; The second is to realize the spatial mapping from the task to the chip to a large extent to complete the calculation. Any computing method that satisfies the above characteristics can be called reconfigurable computing. The first feature shows that reconfigurable computing is programmable after production, so it has the flexibility similar to general-purpose processors; the second feature shows that reconfigurable computing uses space parallel ...

AI Technical Summary

Problems solved by technology

For larger N and M, the circuit complexity can be considered unacceptable

Images