Shipborne Multi-channel Signal Acquisition Synchronous Control System Based on FPGA
A synchronous control, multi-channel signal technology, applied in general control systems, control/regulation systems, program control, etc., to avoid synchronization inconsistencies, solve overhead burdens, and ensure multiple redundancy.
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Embodiment 1
[0043] like Figure 1 to Figure 3 As shown, the FPGA-based shipboard multi-channel signal acquisition synchronous control system, such as figure 1 shown, figure 1 It is a schematic diagram of the structure of the present invention. The system includes:
[0044] 1 clock circuit, N analog IF echo signals, M conditioning circuits, M ADC chips, 1 FPGA, and 1 optical module;
[0045] The clock circuit is used to "sample the clock signal" for the ADC chip;
[0046] M conditioning circuits for preprocessing the N analog IF echo signals introduced;
[0047] M ADC chips are used to perform analog-to-digital conversion processing on multiple preprocessed analog intermediate frequency echo signals under the "sampling clock signal";
[0048] FPGA, used to organize multiple digital intermediate frequency echo signals processed by analog-to-digital conversion into the format data required by the optical module, and send them to the optical module synchronously;
[0049] The clock circui...
Embodiment 2
[0056] like Figure 1 to Figure 3 As shown, the FPGA-based shipboard multi-channel signal acquisition synchronization control system includes:
[0057] 1 clock circuit, 17 or 18 analog IF echo signals, 9 conditioning circuits, 9 ADC chips, 1 FPGA, and 1 optical module; the ADC chip is a dual-channel ADC chip, model: AD9680. Preferably, the FPGA model is: XC7VX690T-2FFG1927I.
[0058] like figure 2 shown, figure 2 The pin connection diagram between FPGA and ADC, SER DOU uses the data transmitted by the transmission channel; the fast detection output pin FD_A or / and the fast detection output pin FD_B of the ADC chip are connected to the FPGA;
[0059] The clock circuit is used to "sample the clock signal" for the ADC chip;
[0060] 9 conditioning circuits for preprocessing the incoming 17 or 18 analog IF echo signals;
[0061] 9 ADC chips are used to perform analog-to-digital conversion processing on multiple preprocessed analog IF echo signals under the "sampling clock s...
Embodiment 3
[0076] preferably,
[0077] When the ADC chip is a single-channel ADC chip, and one ADC chip processes one analog intermediate frequency echo signal into one digital intermediate frequency echo signal;
[0078] FPGA is used to simultaneously observe the multi-frame clock signal waveform in the state waveform of the fast detection output pin FD of all ADC chips. If the multi-frame clock signal waveform of the i-th ADC chip is similar to the multi-frame clock signal waveform of other ADC chips If there is a delay, wait for the output cycle of the i-th ADC chip to complete, and then send the processed data in the required format of the optical module to the optical module to complete the second synchronization.
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