Ship-based multi-channel signal acquisition synchronous control system based on FPGA (Field Programmable Gate Array)
A synchronous control and multi-channel signal technology, applied in general control systems, control/regulation systems, program control, etc., to achieve the effect of verification correction
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Embodiment 1
like Figure 1 to Figure 3 As shown, the FPGA-based shipboard multi-channel signal acquisition synchronous control system, such as figure 1 shown, figure 1 It is a schematic diagram of the structure of the present invention. The system includes:
1 clock circuit, N analog IF echo signals, M conditioning circuits, M ADC chips, 1 FPGA, and 1 optical module;
The clock circuit is used to "sample the clock signal" for the ADC chip;
M conditioning circuits for preprocessing the N analog IF echo signals introduced;
M ADC chips are used to perform analog-to-digital conversion processing on multiple preprocessed analog intermediate frequency echo signals under the "sampling clock signal";
FPGA, used to organize multiple digital intermediate frequency echo signals processed by analog-to-digital conversion into the format data required by the optical module, and send them to the optical module synchronously;
The clock circuit is used to provide the "synchronized second pulse si...
Embodiment 2
like Figure 1 to Figure 3 As shown, the FPGA-based shipboard multi-channel signal acquisition synchronization control system includes:
1 clock circuit, 17 or 18 analog IF echo signals, 9 conditioning circuits, 9 ADC chips, 1 FPGA, and 1 optical module; the ADC chip is a dual-channel ADC chip, model: AD9680. Preferably, the FPGA model is: XC7VX690T-2FFG1927I.
[0029] like figure 2 shown, figure 2 The pin connection diagram between FPGA and ADC, SER DOU uses the data transmitted by the transmission channel; the fast detection output pin FD_A or / and the fast detection output pin FD_B of the ADC chip are connected to the FPGA;
The clock circuit is used to "sample the clock signal" for the ADC chip;
9 conditioning circuits for preprocessing the incoming 17 or 18 analog IF echo signals;
9 ADC chips are used to perform analog-to-digital conversion processing on multiple preprocessed analog IF echo signals under the "sampling clock signal";
FPGA, used to organize multipl...
Embodiment 3
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