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Multi-layer wiring layer structure and preparation method thereof

A technology of multi-layer wiring and layer structure, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc. High density and good trace alignment

Pending Publication Date: 2022-07-05
JCET SEMICON (SHAOXING) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Aiming at the deficiencies in the prior art, the multi-layer wiring layer structure and its preparation method provided by the present invention solve the problem that the wiring precision tends to decrease and the gap between different wiring layers in the prior art exists in the multi-layer wiring layer structure. For the problem of low wiring alignment, the dielectric layer is formed by covering the surface of the uneven metal wiring layer with an adhesive film, which provides a flat base surface for the preparation of the metal wiring layer of the current layer, and the wiring with any layer is obtained Multilayer wiring layer structure with higher density and better alignment

Method used

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  • Multi-layer wiring layer structure and preparation method thereof
  • Multi-layer wiring layer structure and preparation method thereof
  • Multi-layer wiring layer structure and preparation method thereof

Examples

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Embodiment 1

[0036] figure 1 Shown is a schematic flowchart of a method for preparing a multi-layer wiring layer structure provided by an embodiment of the present invention; as figure 1 As shown, the preparation method of the multilayer wiring layer structure specifically includes the following steps:

[0037] In step S101, an n-th dielectric layer having an n-th opening array is prepared.

[0038] In this embodiment, before preparing the first dielectric layer having the first opening array, the method further includes: providing a carrier, and preparing a bonding layer on the carrier.

[0039] In this embodiment, when n=1, a first dielectric layer having a first opening array is prepared by spin-coating a photoresist or a hot-pressing leveling adhesive film, including: on the bonding layer, The first dielectric layer is prepared by spin-coating photoresist or hot-pressing and leveling the adhesive film.

[0040] In this embodiment, when n>1, obtaining an n-th dielectric layer with an...

Embodiment 2

[0070] Figure 11 Shown is a schematic structural diagram of a multi-layer wiring layer structure provided by an embodiment of the present invention, and the n-th layer wiring layer structure sequentially includes:

[0071] an n-th dielectric layer having an array of n-th openings, an n-th seed layer clad on the n-th dielectric layer, and an n-th metal wiring layer disposed on the n-th seed layer ;

[0072] Wherein, n is a positive integer and when n>1, the nth dielectric layer is prepared on the n-1th metal wiring layer by a glue film, and the nth metal wiring layer is sacrificed by photoresist layer to form the opening pattern of the metal wiring.

[0073] In this embodiment, when n=1, the first dielectric layer is prepared by spin-coating a photoresist or a hot-pressing leveling film to obtain a dielectric layer having a first array of openings

[0074] In this embodiment, the multi-layer wiring layer structure further includes: a carrier board, and a bonding layer dispo...

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Abstract

The invention provides a multi-layer wiring layer structure and a preparation method thereof. The method comprises the following steps: preparing an nth dielectric layer with a first opening array; an nth seed layer is prepared on the nth opening array of the nth dielectric layer, so that the nth dielectric layer is coated with the nth seed layer; forming an nth sacrificial layer with an nth opening pattern on the nth seed layer; preparing an nth metal wiring layer in the nth opening pattern of the nth sacrificial layer, and removing the nth sacrificial layer to obtain an nth wiring layer structure; the problems that in the prior art, a wiring layer structure is low in wiring precision of wiring layers and low in wiring alignment degree among different wiring layers are solved, the uneven surface of the upper metal wiring layer is covered with the adhesive film to form the dielectric layer, and a flat base plane is provided for preparation of the current metal wiring layer; and the metal wiring layer structure with higher wiring density of any layer and better wiring alignment is obtained.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a multi-layer wiring layer structure and a preparation method thereof. Background technique [0002] As the market responds to smaller chip sizes and higher integration levels, chip structures tend to be miniaturized, and chip wiring layer structures also tend to be smaller in fabrication size and higher integration levels, while the chip packaging process is subject to Limited by the existing equipment manufacturing capacity and manufacturing cost, in the current relatively high-end chip packaging process, it is necessary to meet the highly integrated packaging of multiple I / O pins of the chip, usually using a fan-out wiring layer structure superimposed with a multi-layer metal wiring layer structure , to realize the multi-layer transmission line wiring of different functional pins of the chip. [0003] However, in the actual process, due to the limitations of t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L23/528H01L23/532
CPCH01L21/76801H01L21/76819H01L21/76877H01L23/5283H01L23/5329
Inventor 潘波李宗怿梁新夫罗富铭唐彬杰杨文豪陶佳强
Owner JCET SEMICON (SHAOXING) CO LTD