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Viterbi deoder

A technology of bit and memory, applied in the field of Viterbi decoder

Inactive Publication Date: 2005-07-20
SHARP KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, when the input bit precision is set to 4 bits, no less than 7 or 8 internal arithmetic bits are required in the add compare select (ACS) part, even with proper normalization

Method used

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Embodiment Construction

[0075] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0076] Fig. 13 is a block diagram showing the construction of a Viterbi decoder according to an embodiment of the present invention. The decoder includes: a branch metric calculator 1, used to calculate the metric between the received sequence and each branch; a bit range converter 11, used to calculate the branch metric value calculated by the branch metric calculator 1 The bit range of is transformed so that it is suitable for the number of calculation bits applied in the plus comparison selection (ACS) part 2; the plus comparison selection (ACS) part 2 is used to select the surviving path and calculate the path metric of the surviving path; the path A metric memory 3 for storing path metric values ​​for each internal state; a path memory 4 for storing estimated outputs of selected paths; and a backtracking processor 5 for detecting the most probable path me...

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Abstract

A Viberbi decoder in which error correction characteristics can be improved while increase of system scale is suppressed. The device is provided with a bit range conversion part for converting the bit range of branch metric values calculated by a branch metric calculation part to match the bit range with the number of bits calculated used for an ACS part, between the calculation part and the ACS part. Until a frame is completed, the received data is read to calculate the branch metric, to optimize the branch metric, to change a path metric, and to store the path metric. When the frame is completed, the result of decoding is outputted by back-tracing.

Description

technical field [0001] The invention relates to a Viterbi decoder which performs bit error correction on received convolutional codes. Background technique [0002] In general, it is known that Viterbi decoding techniques are applied to realize maximum likelihood decoding of convolutional codes. In this Viterbi decoding technology, since the Viterbi decoding algorithm is based on the Viterbi decoding algorithm to select a decoding sequence that is closest to the received code sequence from the code sequences that can be generated by the encoder at the sending end, even if there is a Bit errors can also be decoded correctly. In this way, the Viterbi decoding technique has a high error correction capability for the random bit errors introduced in the communication path. Specifically, this technique can give a large coding gain when combined with soft-decision decoding. Therefore, for mobile communication systems and other systems, Viterbi decoders are widely used in the deco...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/41
CPCH03M13/41H03M13/3961H03M13/4107
Inventor 岸野雅彦
Owner SHARP KK
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