A method for testing a memory array and a memory-based device so testable with a fault response signalizing mode for when finding predetermined correspondence between fault patterns signalizing one su

Abstract

A memory array, and in particular, an embedded memory array is tested by interfacing to a stimulus generator and a response evaluator pair. In a non-test condition the pair is steered in a transparent mode, and in a test condition in a stimulus generating mode and a response evaluating mode respectively. In a subsequent array repair condition row- and / or column-based repair intervention are allowed. In particular, the evaluator will evaluate correspondence between successive fault patterns, and further in a fault response signalizing mode to external circuitry on the basis of a predetermined correspondence between an earlier fault pattern and a later fault pattern signalize one of the two compared patterns only in the form of a lossless compressed response pattern.

Description

technical field [0001] The present invention relates to a method for testing a memory array by pairing a stimulus generator and a response discriminator to said array while directing said pair in a transparent manner when not in a test state, while in a test state The pairing is directed in an excitation generation mode and a response identification mode respectively, and in a subsequent array repair state allows row and / or column intervention repair to be established. Background technique [0002] Single integrated circuit chip memory has grown massively over the years. Mass memory, especially DRAM, suffers from low throughput. It has become common practice to provide memory arrays to repair a faulty array by substituting tested redundant rows and / or columns for defective rows or columns, respectively. In regular manufacturing production, the extra 2% can triple manufacturing volume. Testing of memory has become an elaborate technique, based on current arrays, with many ...

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Problems solved by technology

Therefore, it is often not possible to quickly access the array

[0004] Furthermore, due to the large number of test patterns required, performing a parallel-to-series conversion of the response patterns for internal verification will considerably reduce the test run

On the other hand, restricting a pass / error determination that is not expensive on the chip, for example by a structural way of generating a signature or by a "halt on first error", may not allow repair operations to be performed

[0005] On the other hand, providing full testing and repair of the chip's circuitry is relatively complex and therefore expensive, especially since test results should be provided to the chip indicating various fault locations that require repair

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