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Polishing method and device capable of high precision controlling polishing time

A technology of polishing time and polishing device, which is applied in the fields of mechanical polishing and chemistry, and can solve the problems of increasing wafers, unqualified wafers, and lowering yield.

Inactive Publication Date: 2003-04-23
NEC ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, there is also a problem that not only the number of wafers that need to be re-polished increases, but also defective wafers that cannot be used as products are produced, which reduces the yield.

Method used

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  • Polishing method and device capable of high precision controlling polishing time
  • Polishing method and device capable of high precision controlling polishing time
  • Polishing method and device capable of high precision controlling polishing time

Examples

Experimental program
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Effect test

no. 1 example

[0055] Figure 12 The flow chart of chemical mechanical polishing in this embodiment is shown in . First, the polishing rate of the film material formed on a flat substrate was measured, and then the polishing time of the test wafer was collected. The optimal polishing time is determined based on this data, and the actual wafer to be polished is polished accordingly.

[0056] (i) Polishing objects

[0057] The polishing target wafer of the present embodiment has such Figure 3A The cross-sectional structure shown. In this wafer, an aluminum wiring 2 (film thickness of about 5000 Å) was formed on a silicon wafer, and then a silicon oxide film 3 (film thickness of a flat part of about 14000 Å) was formed by plasma CVD. In this embodiment, a plurality of wafers (a group) of wafers at this stage are prepared, and chemical mechanical polishing is performed for every four wafers. The target film thickness D2 is 5000 Å.

[0058] (ii) Determination of optimal polishing time

[...

no. 2 example

[0079] This embodiment is an example in which wafers having different initial film thicknesses are inserted in the middle of a wafer polishing batch. exist Figure 11 The polishing results are shown in . In the first embodiment, an example of processing several wafers with the same initial film thickness was shown, but in the present embodiment, since wafers with different initial film thicknesses are processed, the polishing time for these wafers is set by another method.

[0080] T'=T+d / v (II) where d is the difference between the initial film thicknesses of the test wafer and the wafer to be polished. In this embodiment, the initial film thickness of the test wafer is about 8700 angstroms. Divide the difference in film thickness of 900 angstroms by the polishing speed v of the flat part obtained in the preliminary experiment, and then add the obtained value to the polishing time t of other trial production numbers, thus obtaining the polishing speed suitable for trial pro...

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Abstract

A preceding wafer having an aluminum wiring and a silicon oxide film formed on an insulating film is chemico-mechanically polished. In the stage in which surface irregularities of the silicon oxide film are eliminated, polishing is discontinued. On the basis of the result, a polishing time is determined in accordance with the following formula: <?in-line-formulae description="In-line Formulae" end="lead"?>T=(D 1- D 2 ) / v+t 1 <?in-line-formulae description="In-line Formulae" end="tail"?> where, D 1 represents the thickness in the stage in which polishing is discontinued; D 2, a target thickness; t 1, a time required from the initial thickness to reach the thickness D 1; and the polishing rate of the material of the silicon oxide film formed on a flat substrate is denoted as v.

Description

technical field [0001] The present invention relates to a chemical and mechanical polishing technique that controls a film formed on a wafer within a predetermined film thickness range and is excellent in film thickness controllability. Background technique [0002] In recent years, along with the miniaturization of semiconductor devices, the importance of technology for flattening the wafer surface has become more and more important. Among them, chemical mechanical polishing (hereinafter referred to as "CMP") occupies a particularly important position in the planarization method because of its excellent productivity and many other advantages. In the CMP process, it is very important to accurately set the conditions for obtaining the target film thickness, especially the setting of the polishing time. [0003] Japanese Patent No. 3077656 discloses a method for correcting a recipe of a semiconductor manufacturing apparatus that does not change the amount of polishing even if...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B24B49/02B24B1/00B24B37/013B24B37/07B24B49/03B24B49/04B24B49/10H01L21/304H01L21/3105
CPCB24B49/03B24B37/042H01L21/31053B24B37/013B24B49/04
Inventor 柿田真一郎
Owner NEC ELECTRONICS CORP