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Semiconductor device

A semiconductor, single crystal semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, transistors, etc., and can solve problems such as high-frequency noise

Inactive Publication Date: 2003-07-09
SANYO ELECTRIC CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this circuit has the disadvantage of generating high-frequency noise when the current is switched, so it must be used shielded from the power supply circuit.

Method used

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  • Semiconductor device
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Embodiment Construction

[0061] Refer below Figure 1 ~ Figure 4 Example 1 of the present invention will be described. First, refer to figure 1 A BICMOS device structure for configuring a charge pump device as an integrated circuit will be described.

[0062] N-channel MOS transistors (NMOS), P-channel MOS transistor (PMOS), NPN bipolar transistor (NPN Tr).

[0063] The N-channel MOS transistor is formed in the P-type well region 52 formed on the surface of the N-type epitaxial silicon layer 51 . The depth of the P-type well region 52 is, for example, about 2 μm. The N-channel MOS transistor has an n+-type drain layer D and an n+-type source layer S formed on the surface of the P-type well region 52, and a gate electrode G formed on the gate insulating film. N-channel type MOS transistors can adopt a so-called LDD structure in order to achieve miniaturization. Further, adjacent to the N-channel MOS transistor, a P+ type layer 53 for biasing the body (well region) is formed on the surface of the...

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Abstract

A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, and a P-type well region is formed in the N-type epitaxial silicon layer. A P+-type buried layer abutting on a bottom of the P-type well region and an N+-type buried layer partially overlapping with the P+-type buried layer and electrically isolating the P-type well region from the single crystalline silicon substrate are formed. And then, an MOS transistor is formed in the P-type well region.

Description

technical field [0001] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device suitable for use in a charge pump device with a large current output used in a power supply circuit and the like, which realizes high performance and prevents latch-up overload. Background technique [0002] In recent years, imaging devices such as video cameras, digital still cameras (DSC), and DSC (digital camera) telephones use CCDs (charge-coupled devices) to capture their images. The CCD drive circuit used to drive the CCD requires a power supply circuit with positive and negative high voltage (+several V) and high current (several mA). Currently, this high voltage is generated using switching regulators. [0003] Switching regulators can generate high voltages with high performance, ie high power efficiency (output power / input power). However, this circuit has the disadvantage of generating high-frequency noise when the current is switched,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/04H01L21/822H01L21/8238H01L21/8249H01L27/02H01L27/06H01L27/092H03K19/0185
CPCH01L27/0222H01L27/0921H01L21/8249H01L21/823892H01L27/0623H01L29/78
Inventor 金子智大古田敏幸名野隆夫
Owner SANYO ELECTRIC CO LTD