Hardware accelerator personality compiler

A loader, deterministic technology used in instrumentation, memory systems, software engineering, etc. to solve problems such as state table difficulty, cost, and reduced error sensitivity

Inactive Publication Date: 2006-05-31
LOCKHEED MARTIN CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

more generally, any situation in which modification of the FSM personality may be required to alter the functionality of a device including the FSM may benefit from a reduction in the difficulty, cost, and error sensitivity of generating the corresponding state table

Method used

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  • Hardware accelerator personality compiler
  • Hardware accelerator personality compiler

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Embodiment Construction

[0022] With reference to the attached drawings, especially the reference figure 1 , figure 1 A high level schematic block diagram showing the basic form of a personality compiler according to the invention and connected to provide a state table to a finite state machine (FSM) in a device, preferably a hardware parser accelerator. Initially, it should be noted that the personality compiler 100 can be implemented as a separate device that can be connected to the memory 105 (such as in the case of a hardware parser accelerator offline), which can then be accessed as needed on a request basis to obtain state transition specification to be loaded by loader 110 into the FSM state table or to be combined with FSM 140 in any device (indicated by dashed line 120) to partially or fully control the state transition specification, thereby allowing a device's personality to be updated in real-time or substantially real-time. It should be appreciated that in the latter case, substanti...

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PUM

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Abstract

A hardware accelerator personality compiler, by distinguishing the marks corresponding to each executable function, logo, variable, syntax, grammatical rules, special symbols, etc. Formal notation provides the specification of a set of expected executable functions, automatically generating error-free state tables. The tokens can be recursive (eg infinite), in which case the tokens are transformed into deterministic finite automata or non-deterministic finite automata. The non-deterministic finite automaton is transformed into a finite automaton and then into state transitions for creating a state table which can then be stored, or preferably loaded into a finite state machine of a hardware parser accelerator , to define its personality.

Description

technical field [0001] The present invention relates generally to application and document processing for controlling the operation of a general-purpose computer, and more particularly to performing parsing operations on sequences of applications, documents and / or other logical symbols in a given but arbitrary language or format. Background technique [0002] The field of digital communication between computers and connecting computers to networks has grown rapidly in recent years, similar in many ways to the proliferation of personal computers in previous years. This increase in the interconnectivity and possibilities of remoting has greatly enhanced the effective capabilities and functionality of individual computers in such networked systems. However, when computers are put into use, the diversity of use of individual computers and systems, the positioning of their users, and the current level of technology result in a high degree of diversity in the capabilities and conf...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/45G06F9/44
CPCG06F8/427
Inventor 迈克尔·C·达普赛·伦·额
Owner LOCKHEED MARTIN CORP
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