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Method for forming storage node of capacitor in semiconductor device

A technology for storage nodes and semiconductors, applied in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve problems such as increased leakage current of capacitors

Active Publication Date: 2006-06-28
CONVERSANT IP N B 868
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, the leakage current of the capacitor increases, causing defects in the semiconductor device

Method used

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  • Method for forming storage node of capacitor in semiconductor device
  • Method for forming storage node of capacitor in semiconductor device
  • Method for forming storage node of capacitor in semiconductor device

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[0030] That is, according to the first embodiment of the present invention, the insulating layer including the contact plug is formed in a stacked structure including a first interlayer insulating layer and a second interlayer insulating layer, and each of the first and second interlayer insulating layers have different etch rates, and the sidewall spacers of the contact plugs are formed by using the same material having the same etch rate as the second interlayer insulating layer. As a result, it is possible to prevent the sidewall spacers from being over-etched during the formation of the second contact hole, that is, the storage node contact hole. As a result, the typically observed occurrence of cracks in the spacers does not occur, thereby improving the step coverage characteristics of the storage node material.

[0031] 3A to 3G are cross-sectional views illustrating a method for forming a capacitor storage node in a semiconductor device according to a second embodiment ...

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Abstract

A method for forming a storage node of a capacitor in a semiconductor device is provided. The method includes the following steps: forming an interlayer insulating layer on a semi-finished substrate; etching the interlayer insulating layer to form a plurality of first contact holes; forming a first insulating layer on the side walls of the first contact holes; forming a plurality of storage node contact plugs filled into the first contact holes; forming a second insulating layer on the storage node contact plugs with an etch rate different from that of the first insulating layer; forming a third insulating layer on the second insulating layer layer; sequentially etching the third insulating layer and the second insulating layer to form a plurality of second contact holes exposing the storage node contact plug; and forming the storage node on each second contact hole.

Description

technical field [0001] The present invention relates to a method for forming a storage node of a capacitor in a semiconductor device; and more particularly, to a method for forming a storage node of a capacitor in a dynamic random access memory device. Background technique [0002] With the high integration of semiconductor devices, the size of unit cells has gradually decreased. Especially in dynamic random access memory (DRAM) devices, a unit cell includes a transistor and a capacitor. Therefore, as the scale of integration of semiconductor devices has increased, it has become much more difficult to control related processes. [0003] A method for forming a storage node of a capacitor in a DRAM device and possible problems associated with this storage formation method will be described below with reference to FIGS. 1A to 1C. [0004] Referring to FIG. 1A, an interlayer insulating layer 11 is formed on a substrate 10 provided with various device elements, and then pattern...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H10B12/00H01L21/768H01L23/522
CPCH01L28/91H01L21/76807H10B12/0335
Inventor 宣俊劦李圣权赵诚允
Owner CONVERSANT IP N B 868