Anti-electrostatic protecting structure by NMOS

A technology of electrostatic protection and protection structure, which is applied in the direction of emergency protection circuit devices, emergency protection circuit devices, circuits, etc. for limiting overcurrent/overvoltage, and can solve the problem of low ESD protection ability of protection tubes, and solve the problem of opening voltage Different effects

Inactive Publication Date: 2007-06-20
SHANGHAI HUA HONG NEC ELECTRONICS
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  • Abstract
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Problems solved by technology

[0003] The technical problem to be solved by the present invention is to provide an anti-static protection structure using NMOS to solve the ESD protection ability caused by t

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  • Anti-electrostatic protecting structure by NMOS
  • Anti-electrostatic protecting structure by NMOS

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Embodiment Construction

[0012] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

[0013] Firstly set forth the inventive idea of ​​the present invention: firstly, the working state of GGNMOS when ESD takes place is first explained, because the base (substrate) of the NPN triode of NMOS parasitic and the PN junction of the emitter (source) should bleed It is in forward conduction, so the bias voltage applied to the base should be 0.7V higher than that of the emitter. This bias voltage is related to the substrate current and the substrate resistance. When the substrate current is constant, the greater the substrate resistance, the greater the substrate resistance. The greater the bias on the base, the earlier the parasitic NPN can be turned on. However, experiments have proved that when ESD occurs, the NMOS parasitic NPN that is always in the center is turned on first, which may result in a low ESD protection capabil...

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Abstract

The invention is concerned with electrostatic-proof protecting structure using NMOS as the basic device of static protecting structure. The number of NMOS is even and is not less than four and adding N well resistance in confined field at the drain area. Set two NMOS at the center of static protecting structure and those grids connect in parallel connection, while the drain pole is in parallel connection. Except the central NMOS, the NMOS drain pole on the both sides is in parallel connection with the central NMOS, and source pole and grid connect with central NMOS in parallel connection and the earth. The source pole of central NMOS connects with the underlay of the parallel NMOS on both sides, i.e. the group pole of parasitical NPN. When the parasitical NPN of central NMOS is expedite, the current distributes to the group poles of parasitical NPN to parallel NMOS on both sides and the group poles are positive expedite with sending pole. This invention solves the problem that protective tube cannot expedite flow equably and the protection ability of ESD is low, when the GGNMOS structure is as the protection of ESD.

Description

technical field [0001] The invention relates to an antistatic circuit structure, in particular to an antistatic protection structure using NMOS. Background technique [0002] The current popular process technology uses CMOS (Complementary Metal-Oxide-Semiconductor Transistor) as an electrostatic discharge (ESD, ElectroStatic Discharge) protection device. When ESD occurs, the discharged electrostatic charge will cause the protection tube Nmos ( The parasitic transistor of N-channel metal-oxide semiconductor (N-channel metal-oxide semiconductor) is turned on, as shown in Figure 3, and a phenomenon of step recovery (Snapback) will occur, as shown in Figure 4; when entering the normal effusion state Before the BC region, the protection tube needs to reach the turn-on voltage of point A. The turn-on voltage is determined by the substrate current and substrate resistance formed by the reverse leakage of the PN junction at the drain end. Because the circuit structure will cause th...

Claims

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Application Information

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IPC IPC(8): H01L23/60H02H9/00
Inventor 金锋苏庆徐向明
Owner SHANGHAI HUA HONG NEC ELECTRONICS
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